中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.015 seconds)

    SWITCH DEVICE
    2.
    发明专利
    SWITCH DEVICE 失效

    公开(公告)号：JP2000115199A

    公开(公告)日：2000-04-21

    申请号：JP24262799

    申请日：1999-08-30

    Applicant: IBM

    Inventor： BLANC ALAIN ,  ORENGO GERARD ,  PORET MICHEL

    IPC: H03M9/00 ,  H04L12/70 ,  H04L12/933 ,  H04L12/935 ,  H04Q11/04 ,  H04L12/28

    Abstract: PROBLEM TO BE SOLVED: To provide the connection switch device of a protocol adapter provided with different speed and format characteristics. SOLUTION: This device is provided with a centralized switch core 10 and a switch core access layer element SCAL. Then, the switch core and the SCAL perform communication through the (n) lines of parallel/serial links for transmitting a logic unit. The SCAL is provided with the (n) pieces of FIFOs, the (n) pieces of RAM storage existing together with respective RAMs related to one logic unit, a first multiplex means for performing a write processing under the control of the first set of the (n) pieces of tables and receiving the contents of a parallel bus and a second multiplex means for performing a read processing from the (n) pieces of the RAM storage under the control of the second set of the (n) pieces of the tables and the logic unit is generated.

    VOLTAGE COMPARATORS WITH LARGE COMMON MODE INPUT VOLTAGE RANGE
    4.
    发明专利
    VOLTAGE COMPARATORS WITH LARGE COMMON MODE INPUT VOLTAGE RANGE 未知

    公开(公告)号：DE3068917D1

    公开(公告)日：1984-09-13

    申请号：DE3068917

    申请日：1980-12-18

    Applicant: IBM ,  IBM FRANCE

    Inventor： ORENGO GERARD ,  VERHAEGHE MICHEL

    IPC: G01R19/165 ,  H03F3/45 ,  H03K5/08 ,  H03K5/24

    Abstract: A voltage comparator circuit with a wide common mode input voltage range which extends beyond supply voltage parameter values. The comparator circuit utilizes an input stage having two input transistors, the emitter electrodes of which are connected to receive input signals and the collector electrodes of which are connected to two current sources. A current fixing circuit is coupled to the collector electrodes of said two input transistors and acts to fix the direct current in the collector circuits at a first value IO and the currents supplied by the current sources at a second value k IO, where k is greater than 2. An output stage is provided with two input circuits respectively connected to the collector electrodes of the two input transistors and with a logic circuit arrangement set to either one of two logic levels in accordance with the sign of the difference in the voltages applied to the pair of emitter electrodes of the two input transistors.

    5.
    发明专利
    未知

    公开(公告)号：DE3881883T2

    公开(公告)日：1993-12-23

    申请号：DE3881883

    申请日：1988-08-30

    Applicant: IBM

    Inventor： CUKIER MAURICE ,  MAUDUIT DANIEL ,  ORENGO GERARD

    IPC: H03M3/04 ,  H03H17/00 ,  H03H17/06 ,  H04L7/033

    Abstract: Digital filter used in a sigma-delta decoder wherein each input sample is involved in the computation of three consecutive PCM output samples. During one sigma-delta sampling period, the filter performs three parallel operations by multiplexing (44) one adder (36) running three times faster than the sigma-delta clock for loading one of three accumulators (38, 40, 42). As the analog-to-digital converter must be kept in phase with remote modem transmit clock, the PCM sampling clock is controlled by the phase tracking performed by adding or subtracting one period of the crystal oscillator from time to time to the PCM sampling clock period. Rotating the order the accumulators are loaded by the adder each PCM sampling time enables to have zero as last coefficient value to add to the accumulator the contents of which is used as PCM output samples. Thus, each PCM sample value is available in the corresponding accumulator one sigma-delta clock period before the last computation. In case of a correction which shortens or lengthens the PCM sampling period, this correction does not change the PCM sample value to be output since the last computation which is either cancelled or repeated, consists in adding zero to the previous accumulator contents.

    7.
    发明专利
    未知

    公开(公告)号：DE69809224T2

    公开(公告)日：2003-08-28

    申请号：DE69809224

    申请日：1998-08-28

    Applicant: IBM

    Inventor： BLANC ALAIN ,  ORENGO GERARD ,  PORET MICHEL

    IPC: H03M9/00 ,  H04Q11/04 ,  H04L12/56

    Abstract: A switching apparatus comprising a centralized Switch Core (10) and at least one SCAL element for the attachment of Protocol Adapters. The Switch Core and the SCAL communicate to each other via n parallel serial links with each one transmitting a Logical Unit. Each SCAL comprises both the receive and the transmit part at least one input for receiving cells from said Protocol Adapter; a set of n FIFO queues (21-25) for storing the cells into n parallel busses; and a set of n RAM storages, with each RAM being associated with one Logical Unit. First multiplexing means (31) receive the contents of the parallel busses for performing simultaneously n WRITE operations into the n RAM storages under control of a first set of n tables ( 36-39). Second multiplexing (41) means are provided for making READ operations from said n RAM storages under control of a second set of n tables ( 46-49). By appropriate arrangement of the two sets of tables, which are chosen complementary, the cells which are conveyed through the first multiplexing means, the RAMs and the second multiplexing means are subject to a cell rearrangement enabling to introduce at least one bitmap field, thereby producing said four Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage (50-80), one particular byte is accidentally stored into one RAM available for a Write operation by means of said first set of tables, thereby causing an alteration to the normal association between said n RAMs and said n Logical Units which is then restablished by said second set of tables.

    8.
    发明专利
    未知

    公开(公告)号：DE68913967D1

    公开(公告)日：1994-04-21

    申请号：DE68913967

    申请日：1989-07-12

    Applicant: IBM

    Inventor： FERRY MICHEL ,  PANTANI JEAN-PIERRE ,  ORENGO GERARD ,  RICHTER GERARD

    IPC: H03M3/02

    Abstract: A sigma-delta converter including a switching component (313) controlled by a first clock (308) having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes means (306, 310, 311) for generating a second clock (350) of a same frequency than the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the swithing element occur during said defined period of time. There is also included means (305) controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses being insensitive to the mismatch of the rise and fall times of said switching element (313) whereby improving the linearity and the signal-to-noise ration of the converter. The control of the said period of time allows the varying of the energy of the pulses in order to provide pulses train which, when applied to a sigma-delta decoder, provides an analog output value representative but attenuated with respect to the analog input value.

    9.
    发明专利
    未知

    公开(公告)号：DE3881883D1

    公开(公告)日：1993-07-22

    申请号：DE3881883

    申请日：1988-08-30

    Applicant: IBM

    Inventor： CUKIER MAURICE ,  MAUDUIT DANIEL ,  ORENGO GERARD

    IPC: H03M3/04 ,  H03H17/00 ,  H03H17/06 ,  H04L7/033

    Abstract: The digital filter has clocking in and out frequencies F and submultiple f respectively, the frequency f being synchronised with a remote clock. The ratio F to f determines the number of taps and accumulators (38,40,42) which add the products to tap coefficients and incoming signals (S1,S2,S3) loaded during each clock cycle at frequency F by processing circuit (32,34,36). The accumulators are clocked out sequentially at frequency f and multiplexer (44) selects the next accumulator to be loaded. A zero value tap ensures the last product output is always zero allowing synchronisation. A clock cycle frequency F may be added or skipped. Frequency f is adjusted by a phase locked loop. Both F . and f are generally derived in a single oscillator.

Patent Agency Ranking