公开(公告)号：GB2581904A

公开(公告)日：2020-09-02

申请号：GB202007034

申请日：2018-10-12

Applicant: IBM

Inventor： ANDREW STEPHEN CASSIDY ,  FILIPP AKOPYAN ,  JOHN VERNON` ARTHUR ,  DHARMENDRA SHANTILAL MODHA ,  PAUL MEROLLA ,  JUN SAWADA ,  MICHAEL VINCENT DEBOLE

IPC: H04L45/02

Abstract: Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.

公开(公告)号：GB2581904B

公开(公告)日：2022-11-16

申请号：GB202007034

申请日：2018-10-12

Applicant: IBM

Inventor： ANDREW STEPHEN CASSIDY ,  FILIPP AKOPYAN ,  JOHN VERNON` ARTHUR ,  DHARMENDRA SHANTILAL MODHA ,  PAUL MEROLLA ,  JUN SAWADA ,  MICHAEL VINCENT DEBOLE

IPC: G06N3/063

Abstract: Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.

公开(公告)号：GB2557780A

公开(公告)日：2018-06-27

申请号：GB201803975

申请日：2017-03-09

Applicant: IBM

Inventor： FILIPP AKOPYAN ,  RODRIGO ALVAREZ-ICAZA ,  JOHN VERNON` ARTHUR ,  ANDREW STEPHEN CASSIDY ,  STEVEN KYLE ESSER ,  BRYAN LAWRENCE JACKSON ,  PAUL MEROLLA ,  DHARMENDRA SHANTILAL MODHA ,  JUN SAWADA

IPC: G06N3/063

Abstract: A multiplexed neural core circuit (100) comprises, for an integer multiplexing factor T that is greater than zero, T sets of electronic neurons, T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons, and a synaptic crossbar or interconnection network (110b) comprising a plurality of electronic synapses that each interconnects a single electronic axon to a single electronic neuron, where the synaptic crossbar or interconnection network (110b) interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons.

公开(公告)号：GB2606600A

公开(公告)日：2022-11-16

申请号：GB202116839

申请日：2021-11-23

Applicant: IBM

Inventor： JUN SAWADA ,  MYRON D FLICKNER ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  PALLAB DATTA ,  DHARMENDRA S MODHA ,  STEVEN KYLE ESSER ,  BRIAN SEISHO TABA ,  JENNIFER KLAMO ,  RATHINAKUMAR APPUSWAMY ,  FILIPP AKOPYAN ,  CARLOS ORTEGA OTERO

IPC: G06N3/04 ,  G06N3/063

Abstract: A neural inference chip is provided, including at least one neural inference core. The at least one neural inference core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of intermediate outputs. The at least one neural inference core comprises a plurality of activation units configured to receive the plurality of intermediate outputs and produce a plurality of activations. Each of the plurality of activation units is configured to apply a configurable activation function to its input. The configurable activation function has at least a re-ranging term and a scaling term, the re-ranging term determining the range of the activations and the scaling term determining the scale of the activations. Each of the plurality of activations units is configured to obtain the re-ranging term and the scaling term from one or more look up tables.

公开(公告)号：GB2557780B

公开(公告)日：2022-02-09

申请号：GB201803975

申请日：2017-03-09

Applicant: IBM

Inventor： FILIPP AKOPYAN ,  RODRIGO ALVAREZ-ICAZA ,  JOHN VERNON` ARTHUR ,  ANDREW STEPHEN CASSIDY ,  STEVEN KYLE ESSER ,  BRYAN LAWRENCE JACKSON ,  PAUL MEROLLA ,  DHARMENDRA SHANTILAL MODHA ,  JUN SAWADA

IPC: G06N3/063

Abstract: A multiplexed neural core circuit according to one embodiment comprises, for an integer multiplexing factor T that is greater than zero, T sets of electronic neurons, T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses that each interconnect a single electronic axon to a single electronic neuron, where the interconnection network interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons.