公开(公告)号：GB2606600A

公开(公告)日：2022-11-16

申请号：GB202116839

申请日：2021-11-23

Applicant: IBM

Inventor： JUN SAWADA ,  MYRON D FLICKNER ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  PALLAB DATTA ,  DHARMENDRA S MODHA ,  STEVEN KYLE ESSER ,  BRIAN SEISHO TABA ,  JENNIFER KLAMO ,  RATHINAKUMAR APPUSWAMY ,  FILIPP AKOPYAN ,  CARLOS ORTEGA OTERO

IPC: G06N3/04 ,  G06N3/063

Abstract: A neural inference chip is provided, including at least one neural inference core. The at least one neural inference core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of intermediate outputs. The at least one neural inference core comprises a plurality of activation units configured to receive the plurality of intermediate outputs and produce a plurality of activations. Each of the plurality of activation units is configured to apply a configurable activation function to its input. The configurable activation function has at least a re-ranging term and a scaling term, the re-ranging term determining the range of the activations and the scaling term determining the scale of the activations. Each of the plurality of activations units is configured to obtain the re-ranging term and the scaling term from one or more look up tables.

公开(公告)号：IL295718B1

公开(公告)日：2024-12-01

申请号：IL29571822

申请日：2022-08-17

Applicant: IBM ,  JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

Inventor： JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

IPC: G06F17/15 ,  G06F17/16

Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

公开(公告)号：GB2606596A

公开(公告)日：2022-11-16

申请号：GB202114616

申请日：2021-10-13

Applicant: IBM

Inventor： ARNON AMIR ,  ANDREW STEPHEN CASSIDY ,  NATHANIEL JOSEPH MCCLATCHEY ,  JUN SAWADA ,  DHARMENDRA S MODHA ,  RATHINAKUMAR APPUSWAMY

IPC: G06N3/063 ,  G06F7/544 ,  G06F9/30 ,  G06N3/04

Abstract: Chips supporting constant time program control of nested loops are provided. In various embodiments, a chip comprises at least one arithmetic-logic computing unit and a controller operatively coupled to the at least one arithmetic-logic computing unit. The controller is configured according to a program configuration, the program configuration comprising at least one inner loop and at least one outer loop. The controller is configured to cause the at least one arithmetic computing unit to execute a plurality of operations according to the program configuration. The controller is configured to maintain at least a first loop counter and a second loop counter, the first loop counter configured to count a number of executed iterations of the at least one outer loop, and the second loop counter configured to count a number of executed iterations of the at least one inner loop. The controller is configured to provide a first indication of whether the first loop counter corresponds to a last iteration and a second indication of whether the second loop counter corresponds to a last iteration. The controller is configured to alternatively increment, reset, or maintain each of the first and second loop counters according to the first and second indications.

公开(公告)号：IL295718B2

公开(公告)日：2025-04-01

申请号：IL29571822

申请日：2022-08-17

Applicant: IBM ,  JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

Inventor： JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

IPC: G06F17/15 ,  G06F17/16

Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

公开(公告)号：IL295718A

公开(公告)日：2022-10-01

申请号：IL29571822

申请日：2022-08-17

Applicant: IBM ,  JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

Inventor： JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

IPC: G06F17/15 ,  G06F17/16

Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

公开(公告)号：GB2604963A

公开(公告)日：2022-09-21

申请号：GB202114617

申请日：2021-10-13

Applicant: IBM

Inventor： ALEXANDER ANDREOPOULOS ,  DHARMENDRA S MODHA ,  CARMELO DI NOLFO ,  MYRON D FLICKNER ,  ANDREW STEPHEN CASSIDY ,  BRIAN SEISHO TABA ,  PALLAB DATTA ,  RATHINAKUMAR APPUSWAMY ,  JUN SAWADA

IPC: G06N3/063 ,  G06F30/3308 ,  G06N3/04

Abstract: Simulation and validation of neural network systems is provided. In various embodiments, a description of an artificial neural network is read. A directed graph is constructed comprising a plurality of edges and a plurality of nodes, each of the plurality of edges corresponding to a queue and each of the plurality of nodes corresponding to a computing function of the neural network system. A graph state is updated over a plurality of time steps according to the description of the neural network, the graph state being defined by the contents of each of the plurality of queues. Each of a plurality of assertions is tested at each of the plurality of time steps, each of the plurality of assertions being a function of a subset of the graph state. Invalidity of the neural network system is indicated for each violation of one of the plurality of assertions.