公开(公告)号：JP2012123797A

公开(公告)日：2012-06-28

申请号：JP2011260006

申请日：2011-11-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DHARMENDRA SHANTIRI MODA ,  STEVE KYLE ESSER ,  GREGORY SEANT CORRADO ,  PAUL A MEROLLA ,  JOHN VERNON ARTHUR

IPC: G06N3/063 ,  G06G7/60 ,  G11C11/54 ,  G11C13/00

CPC classification number: G06N3/049

Abstract: PROBLEM TO BE SOLVED: To provide an integrate-and-fire electronic neuron.SOLUTION: Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated.

Abstract translation: 要解决的问题：提供一体化和消防电子神经元。 解决方案：在接收到外部尖峰信号时，基于外部尖峰信号更新电子神经元的数字膜电位。 膜的电位根据泄漏率衰减。 当膜的电位超过阈值时，产生尖峰信号。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：IL295718B1

公开(公告)日：2024-12-01

申请号：IL29571822

申请日：2022-08-17

Applicant: IBM ,  JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

Inventor： JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

IPC: G06F17/15 ,  G06F17/16

Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

公开(公告)号：GB2606600A

公开(公告)日：2022-11-16

申请号：GB202116839

申请日：2021-11-23

Applicant: IBM

Inventor： JUN SAWADA ,  MYRON D FLICKNER ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  PALLAB DATTA ,  DHARMENDRA S MODHA ,  STEVEN KYLE ESSER ,  BRIAN SEISHO TABA ,  JENNIFER KLAMO ,  RATHINAKUMAR APPUSWAMY ,  FILIPP AKOPYAN ,  CARLOS ORTEGA OTERO

IPC: G06N3/04 ,  G06N3/063

Abstract: A neural inference chip is provided, including at least one neural inference core. The at least one neural inference core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of intermediate outputs. The at least one neural inference core comprises a plurality of activation units configured to receive the plurality of intermediate outputs and produce a plurality of activations. Each of the plurality of activation units is configured to apply a configurable activation function to its input. The configurable activation function has at least a re-ranging term and a scaling term, the re-ranging term determining the range of the activations and the scaling term determining the scale of the activations. Each of the plurality of activations units is configured to obtain the re-ranging term and the scaling term from one or more look up tables.

公开(公告)号：IL295718B2

公开(公告)日：2025-04-01

申请号：IL29571822

申请日：2022-08-17

Applicant: IBM ,  JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

Inventor： JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

IPC: G06F17/15 ,  G06F17/16

Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

公开(公告)号：IL295718A

公开(公告)日：2022-10-01

申请号：IL29571822

申请日：2022-08-17

Applicant: IBM ,  JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

Inventor： JUN SAWADA ,  DHARMENDRA S MODHA ,  ANDREW STEPHEN CASSIDY ,  JOHN VERNON ARTHUR ,  TAPAN KUMAR NAYAK ,  CARLOS ORTEGA OTERO ,  BRIAN TABA ,  FILIPP A AKOPYAN ,  PALLAB DATTA

IPC: G06F17/15 ,  G06F17/16

Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.