公开(公告)号：DE3381270D1

公开(公告)日：1990-04-05

申请号：DE3381270

申请日：1983-11-10

Applicant: IBM

Inventor： FITZGERALD JOSEPH MICHAEL

IPC: H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H03K19/0944 ,  H03K19/173 ,  H01L27/02 ,  H01L23/52 ,  H03K19/00

公开(公告)号：DE3685931D1

公开(公告)日：1992-08-13

申请号：DE3685931

申请日：1986-09-09

Applicant: IBM

Inventor： DUNHAM BRADFORD ,  FITZGERALD JOSEPH MICHAEL ,  WILLIAMS ROBERT RUSSELL

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118

Abstract: A VLSI chip (100) has multiple annular rings (122) of circuit cells, interspersed with annular wiring channels (123) for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area (110) contains all the I/O connections (113) for the chip.

公开(公告)号：DE3884282T2

公开(公告)日：1994-04-21

申请号：DE3884282

申请日：1988-05-03

Applicant: IBM

Inventor： AIPPERSPACH ANTHONY GUS ,  DEWANZ DOUGLAS MICHAEL ,  FITZGERALD JOSEPH MICHAEL

IPC: G06F17/50 ,  G06F15/60

公开(公告)号：DE3685931T2

公开(公告)日：1993-02-25

申请号：DE3685931

申请日：1986-09-09

Applicant: IBM

Inventor： DUNHAM BRADFORD ,  FITZGERALD JOSEPH MICHAEL ,  WILLIAMS ROBERT RUSSELL

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118

Abstract: A VLSI chip (100) has multiple annular rings (122) of circuit cells, interspersed with annular wiring channels (123) for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area (110) contains all the I/O connections (113) for the chip.

公开(公告)号：DE3884282D1

公开(公告)日：1993-10-28

申请号：DE3884282

申请日：1988-05-03

Applicant: IBM

Inventor： AIPPERSPACH ANTHONY GUS ,  DEWANZ DOUGLAS MICHAEL ,  FITZGERALD JOSEPH MICHAEL

IPC: G06F17/50 ,  G06F15/60

公开(公告)号：DE3668517D1

公开(公告)日：1990-03-01

申请号：DE3668517

申请日：1986-09-05

Applicant: IBM

Inventor： FITZGERALD JOSEPH MICHAEL ,  NGUYEN PHO HOANG ,  WILLIAMS ROBERT RUSSELL

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/485 ,  H01L23/52 ,  H01L23/528 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L23/48

Abstract: A VLSI chip (100) has multiple annular rings (122) of circuit cells, interspersed with annular wiring channels (123) for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area (110) contains all the I/O connections for the chip.

公开(公告)号：DE3480136D1

公开(公告)日：1989-11-16

申请号：DE3480136

申请日：1984-12-14

Applicant: IBM

Inventor： AIPPERSPACH ANTHONY GUS ,  FITZGERALD JOSEPH MICHAEL ,  WU PHILIP TUNG

IPC: G11C14/00 ,  G11C7/20 ,  G11C11/00 ,  G11C11/41 ,  G11C11/56 ,  G11C17/12 ,  G11C11/40

Abstract: Static memory cells (11) of an array (1) include FET latches for storing read/write data and transfers FETs having a first or a second threshold voltage for storing read-only data. To recover read/write data from an addressed cell (11), a word-line voltage higher than both threshold voltages is applied to word lines (Wo-Wn) by voltage source means (23). To recover read-only data from the same addressed cell (11), a word-line voltage intermediate the threshold voltages is applied under control of a read-only mode line (211) and the resulting voltages on the bit lines (Bo-Bm, B min o-B min m) are decoded (34). Multiple read-only bits in a single cell (11) are allowed by lowering the cell supply voltage when read-only data are addressed.