公开(公告)号：DE3853182D1

公开(公告)日：1995-04-06

申请号：DE3853182

申请日：1988-07-12

Applicant: IBM

Inventor： CHIN WILLIAM BENEDICT ,  KNEPPER RONALD WILLIAM ,  DUSSAULT RUDOLPH DENNIS ,  WERNICKE FRIEDRIC CHRISTIAN ,  FOON WONG ROBERT CH

IPC: G11C11/41 ,  G11C11/411

Abstract: In a transistor memory cell of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data, the improvement characterized as means for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. This discharging means includes an active device with a forward low-impedance current direction and a reverse high impedance current direction therethrough for each saturation transistor. The active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, the discharging means discharges to a word line at an appropriate potential. In a preferred embodiment, the discharging means discharges to a separate discharge line not connected to the word line. The active devices may be diodes. In yet a further embodiment, the active devices may comprise diodes with leaky reverse bias characteristics. These diodes, in their reverse bias current direction, may be used as the memory cell loads. Alternatively, a PNP transistor may be used as the memory cell load. Resistors may be included in the discharge means to prevent word line-bit line voltage clamping.

公开(公告)号：DE3853182T2

公开(公告)日：1995-09-14

申请号：DE3853182

申请日：1988-07-12

Applicant: IBM

Inventor： CHIN WILLIAM BENEDICT ,  KNEPPER RONALD WILLIAM ,  DUSSAULT RUDOLPH DENNIS ,  WERNICKE FRIEDRIC CHRISTIAN ,  FOON WONG ROBERT CH

IPC: G11C11/41 ,  G11C11/411

Abstract: In a transistor memory cell of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data, the improvement characterized as means for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. This discharging means includes an active device with a forward low-impedance current direction and a reverse high impedance current direction therethrough for each saturation transistor. The active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, the discharging means discharges to a word line at an appropriate potential. In a preferred embodiment, the discharging means discharges to a separate discharge line not connected to the word line. The active devices may be diodes. In yet a further embodiment, the active devices may comprise diodes with leaky reverse bias characteristics. These diodes, in their reverse bias current direction, may be used as the memory cell loads. Alternatively, a PNP transistor may be used as the memory cell load. Resistors may be included in the discharge means to prevent word line-bit line voltage clamping.