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    1.
    发明专利
    未知

    公开(公告)号：DE3853182T2

    公开(公告)日：1995-09-14

    申请号：DE3853182

    申请日：1988-07-12

    Applicant: IBM

    Inventor： CHIN WILLIAM BENEDICT ,  KNEPPER RONALD WILLIAM ,  DUSSAULT RUDOLPH DENNIS ,  WERNICKE FRIEDRIC CHRISTIAN ,  FOON WONG ROBERT CH

    IPC: G11C11/41 ,  G11C11/411

    Abstract: In a transistor memory cell of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data, the improvement characterized as means for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. This discharging means includes an active device with a forward low-impedance current direction and a reverse high impedance current direction therethrough for each saturation transistor. The active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, the discharging means discharges to a word line at an appropriate potential. In a preferred embodiment, the discharging means discharges to a separate discharge line not connected to the word line. The active devices may be diodes. In yet a further embodiment, the active devices may comprise diodes with leaky reverse bias characteristics. These diodes, in their reverse bias current direction, may be used as the memory cell loads. Alternatively, a PNP transistor may be used as the memory cell load. Resistors may be included in the discharge means to prevent word line-bit line voltage clamping.

    5.
    发明专利
    未知

    公开(公告)号：DE2752473A1

    公开(公告)日：1978-06-01

    申请号：DE2752473

    申请日：1977-11-24

    Applicant: IBM

    Inventor： KNEPPER RONALD WILLIAM

    IPC: H03K19/0175 ,  H03K5/02 ,  H03K17/06 ,  H03K17/60 ,  H03K19/017 ,  H03K19/08 ,  H03K19/094 ,  H03K19/0944 ,  H03F3/26 ,  H03F3/16 ,  H03F1/38

    Abstract: Disclosed is a field effect transistor (FET) driver circuit capable of full supply voltage signal swings and high switching speeds while dissipating relatively little power. The output is obtained from a node between two series connected enhancement mode devices. The first of these series connected enhancement mode devices receives an input signal at its gating electrode, while the second of this pair of series connected devices has its gating electrode capacitively coupled to the output node through a first gatable depletion mode device. The first depletion mode device is in a series electrical path with a second depletion mode device and an enhancement mode device. The second depletion mode device and the enhancement mode device in series therewith receive the same phase of the input signal as the gate of said one series connected output transistor while the first gated depletion mode device is either self-biased or gets a gating input that is out of phase therewith. A depletion mode device in parallel with one of the series connected enhancement mode output devices maintains the output node at a full supply voltage level.

    6.
    发明专利
    未知

    公开(公告)号：DE3853182D1

    公开(公告)日：1995-04-06

    申请号：DE3853182

    申请日：1988-07-12

    Applicant: IBM

    Inventor： CHIN WILLIAM BENEDICT ,  KNEPPER RONALD WILLIAM ,  DUSSAULT RUDOLPH DENNIS ,  WERNICKE FRIEDRIC CHRISTIAN ,  FOON WONG ROBERT CH

    IPC: G11C11/41 ,  G11C11/411

    Abstract: In a transistor memory cell of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data, the improvement characterized as means for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. This discharging means includes an active device with a forward low-impedance current direction and a reverse high impedance current direction therethrough for each saturation transistor. The active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, the discharging means discharges to a word line at an appropriate potential. In a preferred embodiment, the discharging means discharges to a separate discharge line not connected to the word line. The active devices may be diodes. In yet a further embodiment, the active devices may comprise diodes with leaky reverse bias characteristics. These diodes, in their reverse bias current direction, may be used as the memory cell loads. Alternatively, a PNP transistor may be used as the memory cell load. Resistors may be included in the discharge means to prevent word line-bit line voltage clamping.

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