公开(公告)号：US3911428A

公开(公告)日：1975-10-07

申请号：US40768173

申请日：1973-10-18

Applicant: IBM

Inventor： CHIN WILLIAM BENEDICT

IPC: G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  H03K19/096 ,  H03M7/00 ,  H03K13/24

CPC classification number: H03K19/0963 ,  G11C8/08 ,  G11C8/10 ,  H03M7/00

Abstract: A decode circuit for use in a decoder employing switches such as complementary metal oxide semiconductor (CMOS) field effect transistors, utilizing cascaded (series-connected) switches of one channel type and a pair of cascoded (parallel-connected) switches of the opposite channel type. In the quiescent state the output lines of the decode circuits are clamped to ground to assure that substantially no power is dissipated. When the decoder system is in the select state, the output lines of the unselected decode circuits remain clamped to ground. The circuit has the advantage that it requires only a pair of cascoded switches plus a strobe switch connected in series with the data switches for operation. This results in a considerable savings of the devices required over prior art decode circuits of this type.

Abstract translation: 一种解码电路，用于采用诸如互补金属氧化物半导体（CMOS）场效应晶体管的开关的解码器，利用一个通道类型的级联（串联）开关和相对通道的一对共源（并联）开关 类型。 在静止状态下，解码电路的输出线被钳位到地，以确保基本上没有功率消耗。 当解码器系统处于选择状态时，未选择的解码电路的输出线保持钳位到地。 该电路的优点是只需要一对级联开关加上与数据开关串联连接的选通开关进行操作。 这导致相对于这种类型的现有技术解码电路所需的器件的可观节省。

公开(公告)号：DE3853182D1

公开(公告)日：1995-04-06

申请号：DE3853182

申请日：1988-07-12

Applicant: IBM

Inventor： CHIN WILLIAM BENEDICT ,  KNEPPER RONALD WILLIAM ,  DUSSAULT RUDOLPH DENNIS ,  WERNICKE FRIEDRIC CHRISTIAN ,  FOON WONG ROBERT CH

IPC: G11C11/41 ,  G11C11/411

Abstract: In a transistor memory cell of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data, the improvement characterized as means for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. This discharging means includes an active device with a forward low-impedance current direction and a reverse high impedance current direction therethrough for each saturation transistor. The active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, the discharging means discharges to a word line at an appropriate potential. In a preferred embodiment, the discharging means discharges to a separate discharge line not connected to the word line. The active devices may be diodes. In yet a further embodiment, the active devices may comprise diodes with leaky reverse bias characteristics. These diodes, in their reverse bias current direction, may be used as the memory cell loads. Alternatively, a PNP transistor may be used as the memory cell load. Resistors may be included in the discharge means to prevent word line-bit line voltage clamping.

公开(公告)号：DE2448099A1

公开(公告)日：1975-04-24

申请号：DE2448099

申请日：1974-10-09

Applicant: IBM

Inventor： CHIN WILLIAM BENEDICT

IPC: G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  H03K19/096 ,  H03M7/00 ,  H03K13/00

Abstract: A decode circuit for use in a decoder employing switches such as complementary metal oxide semiconductor (CMOS) field effect transistors, utilizing cascaded (series-connected) switches of one channel type and a pair of cascoded (parallel-connected) switches of the opposite channel type. In the quiescent state the output lines of the decode circuits are clamped to ground to assure that substantially no power is dissipated. When the decoder system is in the select state, the output lines of the unselected decode circuits remain clamped to ground. The circuit has the advantage that it requires only a pair of cascoded switches plus a strobe switch connected in series with the data switches for operation. This results in a considerable savings of the devices required over prior art decode circuits of this type.

公开(公告)号：DE2320421A1

公开(公告)日：1974-01-03

申请号：DE2320421

申请日：1973-04-21

Applicant: IBM

Inventor： CHIN WILLIAM BENEDICT

IPC: H03K19/0185 ,  H03K19/096 ,  H03K19/08

Abstract: A field-effect transistor logic circuit comprising a plurality of interconnected field-effect transistor devices connected between input and output terminals. A positive feedback path connected between the output terminals and a field-effect transistor device connected to the output terminal is operative to provide an output voltage, VO, which is greater than the supply voltage VS applied to the output device less the threshold voltage VTH of the device, i.e., VO>VS-VTH.

公开(公告)号：DE3853182T2

公开(公告)日：1995-09-14

申请号：DE3853182

申请日：1988-07-12

Applicant: IBM

Inventor： CHIN WILLIAM BENEDICT ,  KNEPPER RONALD WILLIAM ,  DUSSAULT RUDOLPH DENNIS ,  WERNICKE FRIEDRIC CHRISTIAN ,  FOON WONG ROBERT CH

IPC: G11C11/41 ,  G11C11/411

Abstract: In a transistor memory cell of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data, the improvement characterized as means for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. This discharging means includes an active device with a forward low-impedance current direction and a reverse high impedance current direction therethrough for each saturation transistor. The active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, the discharging means discharges to a word line at an appropriate potential. In a preferred embodiment, the discharging means discharges to a separate discharge line not connected to the word line. The active devices may be diodes. In yet a further embodiment, the active devices may comprise diodes with leaky reverse bias characteristics. These diodes, in their reverse bias current direction, may be used as the memory cell loads. Alternatively, a PNP transistor may be used as the memory cell load. Resistors may be included in the discharge means to prevent word line-bit line voltage clamping.

公开(公告)号：DE2356974A1

公开(公告)日：1974-07-04

申请号：DE2356974

申请日：1973-11-15

Applicant: IBM

Inventor： CHIN WILLIAM BENEDICT ,  JEN TEH-SEN

IPC: H03F3/21 ,  H03F3/20 ,  H03F3/213 ,  H03F3/30 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/094

Abstract: An integrated circuit FET push-pull driver includes a first FET boot-strap circuit for charging the driver output node to a value below the driver supply voltage. A second FET boot-strap circuit adds additional charge to the output node to drive the output node to the supply voltage. An FET clamping circuit functions to prevent the additional charge from leaking off through the first boot-strap circuit.