Run-length-limited variable-length coding with error propagation limitation
    1.
    发明授权
    Run-length-limited variable-length coding with error propagation limitation 失效
    运行长度有限可变长度编码与错误传播限制

    公开(公告)号:US3689899A

    公开(公告)日:1972-09-05

    申请号:US3689899D

    申请日:1971-06-07

    Applicant: IBM

    CPC classification number: H03M7/4025 G11B20/1426 H03M7/42

    Abstract: This is a run-length-limited, variable-length coding scheme which reduces the implementation needed to perform encoding and decoding functions and which limits the propagation of framing errors caused by incorrect coding or faulty bit detection. All code words utilized in this scheme are constrained to have distinctive word-ending bit sequences. Word-ending tests are performed repeatedly at strategic points in the bit stream in order to detect bit patterns that may denote word endings, and framing decisions are based upon these tests. Decoding functions are suspended while each new code word or frame is being serially entered into the input register for decoding. Where misframing occurs due to the presence of an erroneous bit in a code word, the propagation of such a framing error through subsequent words is limited by the fact that subsequent word-ending tests are performed independently of the framing decisions that preceded them, and also due to the fact that the average code word length is much less than in a fixed-length code system. Synchronism is quickly restored upon detecting a valid word-ending bit pattern following the erroneous bit. While the code words are of variable length, the rate of data transmission is constant due to a fixed ratio between the number of original data bits and the corresponding encoded data bits.

    Abstract translation: 这是一种运行长度有限的可变长度编码方案,其减少了执行编码和解码功能所需的实现,并且限制了由错误编码或错误位检测引起的成帧错误的传播。 在该方案中使用的所有码字被限制为具有不同的字结束比特序列。 为了检测可能表示单词结尾的位模式,重复执行字尾测试,在位流的策略点进行重复测试,并且框架决策基于这些测试。 解码功能在每个新的代码字或帧被串行输入到输入寄存器进行解码时暂停。 由于在码字中存在错误位而发生错帧,这种帧错误通过后续字的传播受到以下事实的限制:随后的字终止测试独立于它们之前的帧决定执行,并且还 由于平均码字长度远小于固定长度码系统的事实。 检测到错误位之后的有效字尾位模式时,同步快速恢复。 虽然代码字长度可变,但由于原始数据位数与相应的编码数据位之间的固定比例,数据传输速率是恒定的。

    Non-linear filter for delta modulator output using shift register and table lookup
    2.
    发明授权
    Non-linear filter for delta modulator output using shift register and table lookup 失效
    使用移位寄存器和表查找的Δ调制器输出的非线性滤波器

    公开(公告)号:US3916314A

    公开(公告)日:1975-10-28

    申请号:US45893674

    申请日:1974-04-08

    Applicant: IBM

    CPC classification number: H03M3/022

    Abstract: The disclosed delta modulation decoding apparatus responds rapidly to sudden transitions of the delta-modulated signal but avoids excessive noise during periods of no transition. The decoder involves the use of a shift register which receives the incoming delta-modulated code bits and supplies data in parallel to two circuit branches, one containing a delta modulation decoder of any chosen type and the other circuit branch containing a state-responsive, non-linear filter or table, the respective outputs of these two branches being additively combined to provide the decoded and filtered output signal.

    Abstract translation: 所公开的增量调制解码装置快速响应增量调制信号的突变,但避免在无转换期间的过大噪声。 解码器涉及使用移位寄存器,其接收输入的增量调制码比特并且并行提供数据到两个电路分支,一个包含任何选择类型的增量调制解码器,另一个电路分支包含状态响应非 线性滤波器或表,这两个分支的相应输出被相加地组合以提供解码和滤波的输出信号。

    REUSE SPACE RESERVE OF COMPRESSION MEMORY SYSTEM

    公开(公告)号:JP2002132582A

    公开(公告)日:2002-05-10

    申请号:JP2001254088

    申请日:2001-08-24

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a physical memory management system which has free space for storing the contents being held in a compressed form and organized as pages. SOLUTION: The system includes a control apparatus for managing performance of input-output operation of the compressed contents between memory storage devices. Output operation includes memory page-out operation for recovering a free memory storage space. The control apparatus maintains an immediately usable free storage space for recovery to an amount over thresholds so as to perform the page-out operation. A new data structure including position of the page that can be cleared immediately from a physical memory for the page-out operation is provided. The control apparatus accesses the data structure for performing flush operation and conveniently deletes pages more than one identified as being deletable on the list. Based on the data structure and flush operation, the amount of the thresholds for recovering the free storage space is greatly reduced.

    VIRTUAL NON-COMPRESSION CACHE FOR COMPRESSION MAIN MEMORY

    公开(公告)号:JP2000347935A

    公开(公告)日:2000-12-15

    申请号:JP2000135299

    申请日:2000-05-09

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To shorten excessive memory access duration by storing the set of non-compression segments including a virtual non-compression cache arranging all data segments in a memory at random. SOLUTION: In a compression controller 260, respective segments referred to by a directory index 410 of a FIFO are stored in a non-compression format and the set of all these segments forms the virtual non-compression cache and is managed by an expansion control logic 420. Then, the controller 260 checks the status index of a data segment to be accessed for cache error operation, processes any one of compression data segments from a common memory area according to that status and continuously updates a FIFO 410 and the status index of a directory entry corresponding to the time of processing the non- compression data segments. Thus, the data retrieval duration can be shortened.

    METHOD AND DEVICE FOR ADDRESSING CONTENTS OF MAIN MEMORY INCLUDING DIRECTORY STRUCTURE IN COMPUTER SYSTEM

    公开(公告)号:JP2000227874A

    公开(公告)日:2000-08-15

    申请号:JP2000000285

    申请日:2000-01-05

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a system by which a processor can directly access the contents of the main memory of a compression memory system by formatting entries so that address possibility to the prescribed number of entries is given and permitting second directory structure to make a response to a real memory address. SOLUTION: An address for a directory 220 uses the directory (D2) 410 of a second level, which contains plural directory entries formatted so that address possibility to all the directories 220 is supplied. In a directory 410, a directory entry 412 supplies the address possibility of 64c continuous directory entries 420 corresponding to addresses A1-A64 430 in the directory 220. Thus, the memory of 1024 bytes, which contains the directory entry corresponding to addresses A1-A64 430, can be accessed by using an address A0 414.

    SWITCH AND ITS PROTOCOL FOR MAKING DYNAMIC CONNECTIONS

    公开(公告)号:CA2023616C

    公开(公告)日:1995-05-16

    申请号:CA2023616

    申请日:1990-08-20

    Applicant: IBM

    Abstract: A dynamic switch and its protocol for establishing dynamic connections in a link by the use of frames, each frame having an identification of the source of the frame, an identification of the destination of the frame for the requested connection, and link controls to maintain, initiate or terminate a connection between the source and the destination. The frames are bounded by a start of frame delimiter and an end of frame delimiter which may also act as a connect link control and a disconnect link control, respectively, and the onnections are made through the dynamic switch having dynamic-switch ports. The state of a dynamic-switch port is changed dependent on its present state, the dynamic connection requested, and the direction and type of frames passing through the dynamic-switch port.

    RUN-LENGTH-LIMITED VARIABLE-LENGTH CODING WITH ERROR PROPAGATION LIMITATION

    公开(公告)号:CA969670A

    公开(公告)日:1975-06-17

    申请号:CA143830

    申请日:1972-06-05

    Applicant: IBM

    Abstract: This is a run-length-limited, variable-length coding scheme which reduces the implementation needed to perform encoding and decoding functions and which limits the propagation of framing errors caused by incorrect coding or faulty bit detection. All code words utilized in this scheme are constrained to have distinctive word-ending bit sequences. Word-ending tests are performed repeatedly at strategic points in the bit stream in order to detect bit patterns that may denote word endings, and framing decisions are based upon these tests. Decoding functions are suspended while each new code word or frame is being serially entered into the input register for decoding. Where misframing occurs due to the presence of an erroneous bit in a code word, the propagation of such a framing error through subsequent words is limited by the fact that subsequent word-ending tests are performed independently of the framing decisions that preceded them, and also due to the fact that the average code word length is much less than in a fixed-length code system. Synchronism is quickly restored upon detecting a valid word-ending bit pattern following the erroneous bit. While the code words are of variable length, the rate of data transmission is constant due to a fixed ratio between the number of original data bits and the corresponding encoded data bits.

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