Abstract:
This is a run-length-limited, variable-length coding scheme which reduces the implementation needed to perform encoding and decoding functions and which limits the propagation of framing errors caused by incorrect coding or faulty bit detection. All code words utilized in this scheme are constrained to have distinctive word-ending bit sequences. Word-ending tests are performed repeatedly at strategic points in the bit stream in order to detect bit patterns that may denote word endings, and framing decisions are based upon these tests. Decoding functions are suspended while each new code word or frame is being serially entered into the input register for decoding. Where misframing occurs due to the presence of an erroneous bit in a code word, the propagation of such a framing error through subsequent words is limited by the fact that subsequent word-ending tests are performed independently of the framing decisions that preceded them, and also due to the fact that the average code word length is much less than in a fixed-length code system. Synchronism is quickly restored upon detecting a valid word-ending bit pattern following the erroneous bit. While the code words are of variable length, the rate of data transmission is constant due to a fixed ratio between the number of original data bits and the corresponding encoded data bits.
Abstract:
The disclosed delta modulation decoding apparatus responds rapidly to sudden transitions of the delta-modulated signal but avoids excessive noise during periods of no transition. The decoder involves the use of a shift register which receives the incoming delta-modulated code bits and supplies data in parallel to two circuit branches, one containing a delta modulation decoder of any chosen type and the other circuit branch containing a state-responsive, non-linear filter or table, the respective outputs of these two branches being additively combined to provide the decoded and filtered output signal.
Abstract:
PROBLEM TO BE SOLVED: To provide a physical memory management system which has free space for storing the contents being held in a compressed form and organized as pages. SOLUTION: The system includes a control apparatus for managing performance of input-output operation of the compressed contents between memory storage devices. Output operation includes memory page-out operation for recovering a free memory storage space. The control apparatus maintains an immediately usable free storage space for recovery to an amount over thresholds so as to perform the page-out operation. A new data structure including position of the page that can be cleared immediately from a physical memory for the page-out operation is provided. The control apparatus accesses the data structure for performing flush operation and conveniently deletes pages more than one identified as being deletable on the list. Based on the data structure and flush operation, the amount of the thresholds for recovering the free storage space is greatly reduced.
Abstract:
PROBLEM TO BE SOLVED: To provide a device that is coupled to an interconnection network to allow a plurality of hosts to share a collection of memory sectors that store compressed data, in a computer system with a plurality of hosts connected through an interconnection network. SOLUTION: The device includes a network adapter for coupling the device to an interconnection network, a memory for storing a collection of memory sectors, and control logic for managing the memory. The control logic includes a memory compressor/decompressor. The memory further includes a directory for translating a real address of at least one host into an address in the device. A method for managing some memory sectors used by each host, and a method for translating a real address specified by at least one host into a real address of the device are also provided. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To shorten excessive memory access duration by storing the set of non-compression segments including a virtual non-compression cache arranging all data segments in a memory at random. SOLUTION: In a compression controller 260, respective segments referred to by a directory index 410 of a FIFO are stored in a non-compression format and the set of all these segments forms the virtual non-compression cache and is managed by an expansion control logic 420. Then, the controller 260 checks the status index of a data segment to be accessed for cache error operation, processes any one of compression data segments from a common memory area according to that status and continuously updates a FIFO 410 and the status index of a directory entry corresponding to the time of processing the non- compression data segments. Thus, the data retrieval duration can be shortened.
Abstract:
PROBLEM TO BE SOLVED: To provide a system by which a processor can directly access the contents of the main memory of a compression memory system by formatting entries so that address possibility to the prescribed number of entries is given and permitting second directory structure to make a response to a real memory address. SOLUTION: An address for a directory 220 uses the directory (D2) 410 of a second level, which contains plural directory entries formatted so that address possibility to all the directories 220 is supplied. In a directory 410, a directory entry 412 supplies the address possibility of 64c continuous directory entries 420 corresponding to addresses A1-A64 430 in the directory 220. Thus, the memory of 1024 bytes, which contains the directory entry corresponding to addresses A1-A64 430, can be accessed by using an address A0 414.
Abstract:
A dynamic switch and its protocol for establishing dynamic connections in a link by the use of frames, each frame having an identification of the source of the frame, an identification of the destination of the frame for the requested connection, and link controls to maintain, initiate or terminate a connection between the source and the destination. The frames are bounded by a start of frame delimiter and an end of frame delimiter which may also act as a connect link control and a disconnect link control, respectively, and the onnections are made through the dynamic switch having dynamic-switch ports. The state of a dynamic-switch port is changed dependent on its present state, the dynamic connection requested, and the direction and type of frames passing through the dynamic-switch port.
Abstract:
This is a run-length-limited, variable-length coding scheme which reduces the implementation needed to perform encoding and decoding functions and which limits the propagation of framing errors caused by incorrect coding or faulty bit detection. All code words utilized in this scheme are constrained to have distinctive word-ending bit sequences. Word-ending tests are performed repeatedly at strategic points in the bit stream in order to detect bit patterns that may denote word endings, and framing decisions are based upon these tests. Decoding functions are suspended while each new code word or frame is being serially entered into the input register for decoding. Where misframing occurs due to the presence of an erroneous bit in a code word, the propagation of such a framing error through subsequent words is limited by the fact that subsequent word-ending tests are performed independently of the framing decisions that preceded them, and also due to the fact that the average code word length is much less than in a fixed-length code system. Synchronism is quickly restored upon detecting a valid word-ending bit pattern following the erroneous bit. While the code words are of variable length, the rate of data transmission is constant due to a fixed ratio between the number of original data bits and the corresponding encoded data bits.