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    2.
    发明专利
    未知

    公开(公告)号：DE1512874A1

    公开(公告)日：1969-08-14

    申请号：DE1512874

    申请日：1967-06-20

    Applicant: IBM

    Inventor： FRANCIS BEAUSOLEIL WILLIAM ,  MICHAEL MELAS CONSTANTIN

    IPC: H04Q3/00

    Abstract: 1,179,448. Automatic exchange systems. INTERNATIONAL BUSINESS MACHINES CORP. 9 June, 1967 [21 June, 1966], No. 26662/67. Addition to 1,115,520. Heading H4K. The path seeking apparatus of the parent Specification is modified as a result of a more economical expression of the logical functions employed; the logic circuits which examine path co-ordinates, in search of conflict between existing paths and proposed paths, are consequently simplified considerably.

    3.
    发明专利
    未知

    公开(公告)号：DE2212873A1

    公开(公告)日：1972-10-12

    申请号：DE2212873

    申请日：1972-03-17

    Applicant: IBM

    Inventor： FRANCIS BEAUSOLEIL WILLIAM ,  TRENT BROWN DAVID ,  LEE WALKER ERNEST

    IPC: G06F7/78 ,  G11C19/08 ,  G11C19/00

    Abstract: This specification discloses a bubble domain memory in which data is arranged for immediacy of access in accordance with its last use. The memory comprises a plurality of parallel shift registers in which data can be accessed in parallel. In other words, each of the shift registers contains a bit of a page or word so that by the performance of one shifting operation all of the bits of the page or word can be accessed. Data in each shift register is arranged in its order of last use so that the access position K of a shift register having K bit positions contains the last bit of information used and the position K-1 preceding the access position K in the shift register contains the bit of data used just previously to the data in the access position K and so on. In these shift registers the shift positions are arranged in loops for shifting the data between the positions of the shift register. Two such loops are provided, one of the loops contains all the shift positions so that data in any position in the shift register can be shifted into the access position K of the register for reading or writing. The other loop contains all the positions of the shift register but the access position K. This second loop is for reordering the data in the shift register in order of last use after data has been shifted into the access position K for reading or writing by the first loop.

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