公开(公告)号：DE1287339B

公开(公告)日：1969-01-16

申请号：DEJ0027831

申请日：1965-04-03

Applicant: IBM

Inventor： FAIRBANKS SELLERS JUN FREDERIC ,  HOPEWELL JUNCTION ,  TRENT BROWN DAVID

IPC: G11B27/28 ,  G06F13/24 ,  G06F15/78 ,  G11B20/12 ,  G11B20/18 ,  G06F11/10

Abstract: 1,053,174. Error detection and correction. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 9, 1965 [April 6, 1964 (3)], No. 9873/65. Heading G4C. The position of an erroneous bit in an incorrect byte in a group of bytes is detected with the aid of redundancy in each byte and a cyclic redundancy check byte provided for the group of bytes, two byte indications being placed in respective cyclic shift registers and one shifted until a comparison indicates equality, the number of shifts indicating the said position. Data is recorded on magnetic tape as a block of data bytes followed by a cyclic redundancy check (CRC) byte and a longitudinal redundancy check (LRC) byte. Each data byte has internal redundancy (a parity bit, or the number of ONE bits is always the same). The LRC byte provides a parity bit for each track of the tape (i.e. corresponding bit positions in all the other bytes). The mathematical theory of the cyclic checking (CRC) is given in the Specification. During writing on the tape, as the data bytes are sent to the tape, they are also sent to a feedback-connected CRC shift register (CRCR) where each byte is EX-ORed with the present contents of the register and the result shifted one position. When the last data byte has been received, the contents of the CRC register are given one extra shift and then with certain bits complemented, are passed to the tape via a read-write (R/W) register as the CRC byte. Then the LRC byte is recorded on the tape. The bytes are read again concurrently with the writing operation, and vertical redundancy checks (VRC, the internal redundancy of each byte) and LRC performed. During reading from the tape, the bytes are transferred via the R/W register to the CRCR (except the LRC byte) and a VRC is performed on each byte. In detection of a VRC error, a ONE is entered in a feedback-connected error pattern register (EPR) which is being shifted in synchronism with the CRCR. If a CRC, VRC or LRC error has occurred during reading, the tape is backspaced and the track in error determined as follows. The contents of the EPR are transferred to the R/W register (previously cleared) and a ONE inserted in the top position of the EPR (otherwise clear). The EPR and CRCR are shifted together until the contents of the CRCR equal those of the R/W register, as determined by an all ZEROES output from EX-OR gates 16 (Fig. 2, not shown). The position of the ONE bit in the EPR then gives the track in error, and the CRCR is reset. A second reading of the tape commences and on detection of a VRC error in a byte, the contents of the EPR are supplied to the EX-OR gates 16 (not shown) through which the tape byte is passing to complement the bit which is in the erroneous channel. The bytes, after correction, are sent to the CRCR. When all the bytes have been received, the CRCR is sampled for a CRC error. Also, an LRC register (LRCR) which received the uncorrected bytes is sampled for an LRC error, positions in which an error correction took place being ignored for this purpose. Backwards read may be performed by reversing directions of shift or having reversible input connections.

公开(公告)号：DE2212873A1

公开(公告)日：1972-10-12

申请号：DE2212873

申请日：1972-03-17

Applicant: IBM

Inventor： FRANCIS BEAUSOLEIL WILLIAM ,  TRENT BROWN DAVID ,  LEE WALKER ERNEST

IPC: G06F7/78 ,  G11C19/08 ,  G11C19/00

Abstract: This specification discloses a bubble domain memory in which data is arranged for immediacy of access in accordance with its last use. The memory comprises a plurality of parallel shift registers in which data can be accessed in parallel. In other words, each of the shift registers contains a bit of a page or word so that by the performance of one shifting operation all of the bits of the page or word can be accessed. Data in each shift register is arranged in its order of last use so that the access position K of a shift register having K bit positions contains the last bit of information used and the position K-1 preceding the access position K in the shift register contains the bit of data used just previously to the data in the access position K and so on. In these shift registers the shift positions are arranged in loops for shifting the data between the positions of the shift register. Two such loops are provided, one of the loops contains all the shift positions so that data in any position in the shift register can be shifted into the access position K of the register for reading or writing. The other loop contains all the positions of the shift register but the access position K. This second loop is for reordering the data in the shift register in order of last use after data has been shifted into the access position K for reading or writing by the first loop.

公开(公告)号：DE1449802A1

公开(公告)日：1968-12-05

申请号：DE1449802

申请日：1964-12-23

Applicant: IBM

Inventor： TRENT BROWN DAVID ,  FAIRBANKS SELLERS JUN FREDERIC

IPC: G11B20/14