公开(公告)号：GB2500081B

公开(公告)日：2014-02-19

申请号：GB201223293

申请日：2012-12-21

Applicant: IBM

Inventor： FREDICKSON MARK S ,  FREI SCOTT D ,  MCBRIDE CHAD B ,  BELLOWS MARK D ,  JONES STEVEN P

IPC: G06F11/16

公开(公告)号：GB2500081A

公开(公告)日：2013-09-11

申请号：GB201223293

申请日：2012-12-21

Applicant: IBM

Inventor： FREDICKSON MARK S ,  FREI SCOTT D ,  MCBRIDE CHAD B ,  BELLOWS MARK D ,  JONES STEVEN P

IPC: G06F11/16

Abstract: A method comprises receiving first processor input 124 at a first FIFO (first-in first-out) memory 142 from a first processor group 112 that comprises a first processor 114 and is configured to execute program code 118 based on the first processor input, storing the first processor input at the first FIFO memory, outputting it to a second FIFO memory 152 and, according to a first delay, to a second processor 148, executing at the second processor at least a first portion of the program code, storing the first processor input at the second FIFO memory, outputting it, according to a second delay, to a third processor 158, and executing at the third processor at least a second portion of the program code. A system 100 and removable computer card 130 are also provided. Delayed lockstep processing may be used to detect an error in a processor, and for debug analysis (Figure 7).