公开(公告)号：JPH10241399A

公开(公告)日：1998-09-11

申请号：JP3608898

申请日：1998-02-18

Applicant: IBM

Inventor： KALTER HOWARD L ,  JOHN EDWARD BASS JR ,  JEFFREY HARRIS DOREIBERUBISU ,  REX NUGO KOO ,  MORI YOTARO ,  JOHN STEWART PARENTEU JR ,  DONALD LAURENCE WEETER

IPC: G01R31/28 ,  G06F11/273 ,  G11C29/02 ,  G11C29/12 ,  G11C29/32 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a built-in self test BIST macro of a processor base for testing a dynamic random access memory(DRAM) built in a logic chip. SOLUTION: A BIST macro 200 is provided with two ROMs in a sequencer 205, a first ROM is made a ROM for storing a test instruction, a second ROM is made a ROM for scanning, so as to perform sequencing of a test instruction stored in the first ROM as well as a branching function and a loop function. Further, the BIST macro 200 monitors obstacle in a DRAM, and is provided with a redundant allotting logic section 260 for exchanging an obstacle word line or a data line, or the both.

公开(公告)号：JP2000003590A

公开(公告)日：2000-01-07

申请号：JP341899

申请日：1999-01-08

Applicant: IBM

Inventor： BARTH JOHN E ,  DREIBELBIS JEFFREY H ,  KALTER HOWARD L

IPC: G11C11/417 ,  G06F12/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To improve the performance of a buried memory macro device by making added information communicated between a storage device and a logic circuit. SOLUTION: This buried memory macro device comprises a storage device 12 and a logic circuit 10 constituted on a common semiconductor substrate. The storage device and the logic circuit communicate with each other using a handshake procedure through a system data interlock signal 26. During a reading cycle. The storage device informs the logic circuit when data in data output of the storage device effective by utilizing the system data interlock signal during a reading cycle, and the storage device informs the logic circuit whether data have been written well by utilizing the system data interlock signal during a writing cycle. After that, the logic circuit instructs the storage device to reset the system interlock signal to make it possible to start instantly new reading or writing.

公开(公告)号：JPH11213700A

公开(公告)日：1999-08-06

申请号：JP1657598

申请日：1998-01-29

Applicant: IBM

Inventor： KALTER HOWARD L ,  JOHN EDWARD BASS JR ,  JEFFREY HARRIS DOREIBERUBISU ,  REX NUGO KOO ,  MORI YOTARO ,  JOHN STEWART PARENTEU JR ,  DONALD LAURENCE WEETER

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12

Abstract: PROBLEM TO BE SOLVED: To provide a built-in self inspection(BIST) for a processor base for testing a dynamic random access memory(DRAM) built in a logic chip. SOLUTION: A BIST 200 has two ROMs(read only memories) in a sequencer 205. One is to store test commands and the other is a ROM that can be scanned and provides not only a branch function and a loop function, but sequencing of test commands stored in the first ROM. A BIST macro has further a redundant allocation logic section 260 which monitors faults in a DRAM and exchanges a fault word line or a fault data line or both lines.

公开(公告)号：CA2034027C

公开(公告)日：1995-12-19

申请号：CA2034027

申请日：1991-01-11

Applicant: IBM

Inventor： BARTH JOHN E JR ,  DRAKE CHARLES E ,  FIFIELD JOHN A ,  HOVIS WILLIAM P ,  KALTER HOWARD L ,  LEWIS SCOTT C ,  NICKEL DANIEL J ,  STAPPER CHARLES H ,  YANKOSKY JAMES A

IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

Abstract: A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by-carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：DE3865152D1

公开(公告)日：1991-10-31

申请号：DE3865152

申请日：1988-06-28

Applicant: IBM

Inventor： ADAMS ROBERT D ,  FLAKER ROY C ,  GRAY KENNETH S ,  KALTER HOWARD L

IPC: H03K17/08 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0948

Abstract: A CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor (32) arranged in series with a second or pull-up P-channel transistor (30) and a third P-channel transistor (36) connected from the common point (B) between the first and second transistors (32, 30) and the gate electrode of the first transistor (32). The first and second transistors (32, 30) are disposed between a data output terminal (24) and a first voltage source (28) having a supply voltage of a given magnitude, with the data output terminal (24) also being connected to a circuit or system including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. In a more specific aspect of this invention, a fourth P-channel transistor (38), disposed in a common N-well (40) with the other P-channel transistors, is connected at its source to the first voltage source (28) and at its drain to the common N-well, with its gate electrode being connected to the data output terminal.

公开(公告)号：CA2034027A1

公开(公告)日：1991-08-14

申请号：CA2034027

申请日：1991-01-11

Applicant: IBM

Inventor： BARTH JOHN E JR ,  DRAKE CHARLES E ,  FIFIELD JOHN A ,  HOVIS WILLIAM P ,  KALTER HOWARD L ,  LEWIS SCOTT C ,  NICKEL DANIEL J ,  STAPPER CHARLES H ,  YANKOSKY JAMES A

IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：CA2024638C

公开(公告)日：1995-04-25

申请号：CA2024638

申请日：1990-09-05

Applicant: IBM

Inventor： DRAKE CHARLES E ,  KALTER HOWARD L ,  LEWIS SCOTT C

IPC: H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948

Abstract: A CMOS integrated circuit for driving capacitance devices is provided. The circuit has an input node and an output node and includes a first transistor operatively connected to the input node which is turned "on" and "off" by the input node to supply an output signal to the output node when turned "on". A second transistor is provided, the output of which is connected to the output node when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor prior to the second transistor, and to turn on the second transistor if and only if the slew rate of the output signal of the first transistor is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor; however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor will cause the second transistor to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

公开(公告)号：CA2002362C

公开(公告)日：1994-02-01

申请号：CA2002362

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L ,  LO TIN C

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/22 ,  G06F11/00

Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH LOCK-UP FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：CA2002361C

公开(公告)日：1993-12-21

申请号：CA2002361

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/22 ,  G06F11/00

Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH DISABLEMENT FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：DE69921708T2

公开(公告)日：2005-11-03

申请号：DE69921708

申请日：1999-01-14

Applicant: IBM

Inventor： BARTH JOHN E ,  DREIBELBIS JEFFREY H ,  KALTER HOWARD L

IPC: G11C11/417 ,  G06F12/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

Abstract: An embedded memory macro device includes a memory system and a logic circuit constructed on a common semiconductor substrate. The memory system and logic circuit communicate through a handshake procedure via a system data interlock signal. During read cycles the memory system uses the system data interlock signal to tell the logic circuit when data at memory system data outputs is valid. In the preferred embodiment, during write cycles the memory system uses the system data interlock signal to tell the logic circuit when data has been successfully written. The logic circuit needs to wait only until the system data interlock signal permits it to proceed. It then signals the memory system to reset the system data interlock signal and can immediately initiate a new read or write cycle.