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    METHOD OF MANUFACTURING A CONDUCTOR STRUCTURE AND APPLICATION IN A FIELD EFFECT TRANSISTOR
    1.
    发明专利
    METHOD OF MANUFACTURING A CONDUCTOR STRUCTURE AND APPLICATION IN A FIELD EFFECT TRANSISTOR 未知

    公开(公告)号：DE2861516D1

    公开(公告)日：1982-02-25

    申请号：DE2861516

    申请日：1978-10-04

    Applicant: IBM

    Inventor： GAENSSLEN FRITZ HEINRICH

    IPC: H01L29/78 ,  H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L23/532 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L21/88 ,  H01L21/60 ,  H01L29/76 ,  H01L23/52

    Abstract: A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated circuits as well as other integrated structures. In the method a first layer of polysilicon is deposited followed by a deposition of a metal of the silicide forming type. Another polysilicon layer is then deposited on top of the silicide forming metal to produce a three layer structure. The three layer structure is subjected to heat, for example, during the reoxidation step in a gate fabrication process, the metal reacts with the polysilicon at two reaction fronts to form a silicide. The resultant silicide has a much lower resistivity than doped polysilicon and therefore provides a second conductive layer which can be used more compatibly and efficiently in connection with the normal metal layer employed in integrated circuits to give a two-dimensional degree of freedom for the distribution of signals.

    3.
    发明专利
    未知

    公开(公告)号：DE2363089A1

    公开(公告)日：1974-07-04

    申请号：DE2363089

    申请日：1973-12-19

    Applicant: IBM

    Inventor： GAENSSLEN FRITZ HEINRICH ,  KRICK PAUL JOHN

    IPC: G11C11/405 ,  G11C11/403 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  G11C11/24

    Abstract: A semiconductor two device memory cell is disclosed in which the two devices are complementary. The cell is best implemented in the integrated circuit environment and may be fabricated using well known non-complementary fabrication techniques. The cell incorporates a floating region or substrate - within - a - substrate on which charge is stored in different amounts to achieve different potentials on the region thereby controlling, in one mode, the threshold of a field effect transistor of which the floating region forms a part. In a different mode, the floating region or substrate forms a drain or source region for a switching transistor which is formed in its own substrate. The latter substrate, which is formed from a semiconductor chip or wafer, besides forming the channel region of the switching transistor acts as a source for a sensing transistor which is formed by a region of opposite conductivity type in the floating region, the floating region and the substrate itself. The floating region is charged to one of two potentials when the floating region is a drain or source of the switching transistor and, the amount of current flow is controlled by the potential on the floating region when it operates as the substrate for the sensing transistor.

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