公开(公告)号：BR8903161A

公开(公告)日：1990-02-06

申请号：BR8903161

申请日：1989-06-28

Applicant: IBM

Inventor： GALLAGHER PATRICK WAYNE ,  GREGOR STEVEN LEE ,  REEVE STEPHEN MICHAEL

IPC: G06F12/08 ,  G06F13/14

Abstract: Multi level cache storage system for a multiprocessor system in which each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors. The multiprocessors share the level two cache according to a priority algorithm. When data in the level two cache is updated, corresponding data in level one caches is invalidated until it is updated.

公开(公告)号：DE19516937A1

公开(公告)日：1995-12-07

申请号：DE19516937

申请日：1995-05-09

Applicant: IBM

Inventor： BISHOP JAMES WILSON ,  CARMACK JUN CHARLES EMBRY ,  GALLAGHER PATRICK WAYNE ,  JACKOWSKI STEFAN PETER ,  KLOUDA GREGORY ROBERT ,  SIEGL ROBERT DWIGHT

IPC: G06F12/08

Abstract: The hierarchical cache system includes a number of cache sub-systems for storing data or instructions of various central units (ZEs), a cache sub-system of a level (S2) higher than a first level (S1) and a main store connected to the higher level (S2) cache sub-system. A data transfer device is connected to the S2 cache and to the main store, and stores a ZE data to main store, without copying the earlier contents of a store request in-address into the S2 cache as an response to the request, and for invalidating the earlier contents in the cache sub-system (S2), if it already resides there, as the ZE makes the request.