公开(公告)号：DE3871404D1

公开(公告)日：1992-07-02

申请号：DE3871404

申请日：1988-01-12

Applicant: IBM

Inventor： JACKOWSKI STEFAN PETER ,  JENKINS RONALD BRIAN

IPC: G06F11/10 ,  G06F11/267 ,  H03M13/00

Abstract: A system for verifying proper operation of a checking code generator (16, 30) is provided. A means (18, 32) is operatively connected to the checking code generator. The verification is done by converting a checking code generated by the checking code generator to data for further processing thereof in order to exercise the checking code generator.

公开(公告)号：AT30783T

公开(公告)日：1987-11-15

申请号：AT84105935

申请日：1984-05-25

Applicant: IBM

Inventor： JACKOWSKI STEFAN PETER ,  MOYER JAMES THEODORE

IPC: G06F13/00 ,  G01R31/28 ,  G06F11/00 ,  G06F11/16 ,  G06F13/36

Abstract: Testing of interface lines (14) interconnecting a first circuit (10) to a second circuit. When an abnormal circuit condition affects the interface lines, such as an open circuit or a short circuit condition, the operation of the first and second circuit is detrimentally affected. The present invention determines the existence of abnormal circuit conditions in one or more lines of a group of interface lines without the utilization of redundant duplex lines to perform the determination. The interface lines are subdivided into a first group (14a), which are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, and a second group (14b), which is not used when the apparatus of the present invention is being used to locate abnormal circuit conditions. Each line of the first group is connected to a corresponding input terminal of a first exclusive OR gate (16) and a second exclusive OR gate (18) at an input side and an output side, respectively. The first and second OR gates are input to a matching circuit (20), an output signal therefrom indicating the existence of an abnormal circuit condition in the first group of lines. As a result, since the lines of the first group are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, each line of the first group is tested individually for the presence of an abnormal circuit condition. However, since the lines of the second group are not used when the apparatus of the present invention is locating abnormal circuit conditions, the lines of the second group are tested, collectively, as a group, for the presence of an abnormal circuit condition. One line (11) of the first group is connected to an input side of the second group. The output side of the second group is connected to an additional input terminal of the second exclusive OR gate. An output signal from the matching circuit indicates the existence of an abnormal circuit condition in at least one line of either one or both of the first and second group of lines.

公开(公告)号：DE68924051D1

公开(公告)日：1995-10-05

申请号：DE68924051

申请日：1989-11-16

Applicant: IBM

Inventor： JACKOWSKI STEFAN PETER ,  JENKINS RONALD BRIAN

IPC: G06F13/14 ,  G06F13/00 ,  G06F13/12

公开(公告)号：DE3484634D1

公开(公告)日：1991-07-04

申请号：DE3484634

申请日：1984-06-15

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  JACKOWSKI STEFAN PETER ,  MOYER JAMES THEODORE ,  PLANT III JAMES WALTER

IPC: H04L1/00 ,  G06F11/10

Abstract: A failure detection apparatus is disclosed for detecting the existence of abnormal circuit conditions in a circuit, the abnormal condition causing erroneous data to be transmitted from one circuit to another circuit, via interface lines. Since spare interface lines are not available, the existing interface lines (11) must be used to determine the accuracy of the transmitted data. A gate line (13), interconnecting adjacent intergrated circuits (10, 12), gates the odd and the even data bytes of the data from the one adjacent integrated circuit to another. If the gate line fails, or otherwise experiences an abnormal circuit condition, the odd and the even data bytes will not be gated from the one adjacent integrated circuit to the other in the proper sequence. With the present invention, the proper sequence is checked. The even data bytes are transmitted along the existing interface lines from the one adjacent integrated circuit to the other with an odd parity; however, the odd data bytes are transmitted along the existing interface lines with an even parity. The receiving integrated circuit determines whether the even data bytes were received with the odd parity and whether the odd data bytes were received with the even parity. An error signal is generated when the even and odd data bytes are not received with the odd and even parity, respectively. The error signal indicates the existence of the failure gate line.

公开(公告)号：DE3467418D1

公开(公告)日：1987-12-17

申请号：DE3467418

申请日：1984-05-25

Applicant: IBM

Inventor： JACKOWSKI STEFAN PETER ,  MOYER JAMES THEODORE

IPC: G06F13/00 ,  G01R31/28 ,  G06F11/00 ,  G06F11/16 ,  G06F13/36

Abstract: Testing of interface lines (14) interconnecting a first circuit (10) to a second circuit. When an abnormal circuit condition affects the interface lines, such as an open circuit or a short circuit condition, the operation of the first and second circuit is detrimentally affected. The present invention determines the existence of abnormal circuit conditions in one or more lines of a group of interface lines without the utilization of redundant duplex lines to perform the determination. The interface lines are subdivided into a first group (14a), which are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, and a second group (14b), which is not used when the apparatus of the present invention is being used to locate abnormal circuit conditions. Each line of the first group is connected to a corresponding input terminal of a first exclusive OR gate (16) and a second exclusive OR gate (18) at an input side and an output side, respectively. The first and second OR gates are input to a matching circuit (20), an output signal therefrom indicating the existence of an abnormal circuit condition in the first group of lines. As a result, since the lines of the first group are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, each line of the first group is tested individually for the presence of an abnormal circuit condition. However, since the lines of the second group are not used when the apparatus of the present invention is locating abnormal circuit conditions, the lines of the second group are tested, collectively, as a group, for the presence of an abnormal circuit condition. One line (11) of the first group is connected to an input side of the second group. The output side of the second group is connected to an additional input terminal of the second exclusive OR gate. An output signal from the matching circuit indicates the existence of an abnormal circuit condition in at least one line of either one or both of the first and second group of lines.

公开(公告)号：DE68924051T2

公开(公告)日：1996-05-02

申请号：DE68924051

申请日：1989-11-16

Applicant: IBM

Inventor： JACKOWSKI STEFAN PETER ,  JENKINS RONALD BRIAN

IPC: G06F13/14 ,  G06F13/00 ,  G06F13/12

公开(公告)号：DE19516937A1

公开(公告)日：1995-12-07

申请号：DE19516937

申请日：1995-05-09

Applicant: IBM

Inventor： BISHOP JAMES WILSON ,  CARMACK JUN CHARLES EMBRY ,  GALLAGHER PATRICK WAYNE ,  JACKOWSKI STEFAN PETER ,  KLOUDA GREGORY ROBERT ,  SIEGL ROBERT DWIGHT

IPC: G06F12/08

Abstract: The hierarchical cache system includes a number of cache sub-systems for storing data or instructions of various central units (ZEs), a cache sub-system of a level (S2) higher than a first level (S1) and a main store connected to the higher level (S2) cache sub-system. A data transfer device is connected to the S2 cache and to the main store, and stores a ZE data to main store, without copying the earlier contents of a store request in-address into the S2 cache as an response to the request, and for invalidating the earlier contents in the cache sub-system (S2), if it already resides there, as the ZE makes the request.