公开(公告)号：JP2000181886A

公开(公告)日：2000-06-30

申请号：JP34017199

申请日：1999-11-30

Applicant: IBM

Inventor： GARY DALE CARPENTER ,  PHILIPPE LOUIS DEBACKER ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO ,  RONALD RIN ROCKHOLD

IPC: G06F15/173 ,  G06F9/48 ,  G06F15/177 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To obtain an interruption processing mechanism equipped with an efficient mechanism for the path specification and transmission of interruption by incorporating a processor which receives external interruption and an interruption source which generate the external interruption. SOLUTION: An NUMA computer system 6 includes plural process nodes 8a to 8n which are interconnected through node interconnection 22. Each memory controller 17 includes an interruption destination unit(IDU) 19. The IDU 19 includes plural registers and logic units which facilitate the path specification and process of interruption. An input/output device 32 and a storage device 34 generate interruptions for a notice of the reception of an input value and a report on error conditions through an interruption request line 35. These external interruptions are collected by interruption source units(ISU) 28a and 28b. The ISU 28 allocates the path of an external interruption to the IDU 19, which passes the external interruption and other interruptions to a local processor 10 through an interruption request line 36 for processing.