公开(公告)号：JP2000250883A

公开(公告)日：2000-09-14

申请号：JP2000045925

申请日：2000-02-23

Applicant: IBM

Inventor： JOHN PATON BANNISTER ,  CARPENTER GARY DALE ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO ,  RICHARD NICHOLAS IACHETTA JR

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To avoid the loss of data and coherence by respectively providing first and second nodes with a local mutual connection, a system memory coupled with the local mutual connection and a node controller located between the local mutual connections. SOLUTION: A READ request in a home node 10a is transferred to a remote node 10b where corrected data are resident. Concerning the READ request, the boat of correction/intervention is received by the remote node 10b. The remote node 10b returns the corrected/intervened boat and the corrected data to the home node 10a. A node controller 20 generates a new tag and issue the write back kill (WBC request) of R bit = 1. A coherence mechanism in the node controller 20 completes the WBC request like ReRum of locally generated WBC requests. In this case, data in a local memory 18 are made effective.

公开(公告)号：JP2000250882A

公开(公告)日：2000-09-14

申请号：JP2000045824

申请日：2000-02-23

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To avoid a lie block by completing any one of two requests in response to a request from the processor of a first node so as to invalidate the remote copy of a cache line stored in a cache memory. SOLUTION: A first request is selected so as to win (namely, Retry is not received yet). When an invalidation request is transferred to a requested remote node by a node controller 19 on the side of home node, a special bit called AutoRetry bit is set in a transaction. Read (RWITM) intending a correction from the home node 11 is repeated on the side of remote node 12 and Retry is locally performed. When Dclaim request from the remote node 12 is tried again back to a processor 24a, the opportunity to efficiently complete the RWITM request from the home node 11 on a local bus in the remote node 12 is increased.

公开(公告)号：JP2000250881A

公开(公告)日：2000-09-14

申请号：JP2000045748

申请日：2000-02-23

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DAVID BRIAN GRASCO

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To avoid lie block conditions by completing write back on the side of home node without retry only in the case of write back from the owned node of a corrected cache line by a coherence directory in the home node. SOLUTION: The cache coherence directory in a node controller 19 on the side of node 11 can be constructed so as to fetch back a cache line from the owned node for a non-processed request and to simultaneously discriminate time to receive a write back kill (WBC request) from the owned node of the cache line. A READ request is issued again by a processor 14a on the side of home node 11, a system memory 17 supplies effective data and the READ request is efficiently completed by a clean response. The lie block conditions can be avoided. Since the system memory 17 is updated into effective data by the WBC request, data can be supplied.

公开(公告)号：JP2000250884A

公开(公告)日：2000-09-14

申请号：JP2000045976

申请日：2000-02-23

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO

IPC: G06F9/52 ,  G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To improve a method for evicting a cache line from a loose directory by writing data from a corrected cache line back to the local system memory of a node and evicting an entry from the loose directory later. SOLUTION: First of all, when corrected data are tried to return to the system memory, a correction intended read (RWITM) transaction can be tried again by any reason except the generation of retry by a processor. In this case, the RWITM transaction is forcedly issued again to a transaction reception unit by an AutoRetry mode. Secondly, it is possible for a corrected cache line to be absent in the remote node 10b and RWITM receives an erasure response. Afterwards, the transaction reception unit of a node controller 20b returns a response to an eviction logic and completes the eviction.

公开(公告)号：JP2000181886A

公开(公告)日：2000-06-30

申请号：JP34017199

申请日：1999-11-30

Applicant: IBM

Inventor： GARY DALE CARPENTER ,  PHILIPPE LOUIS DEBACKER ,  MARK EDWARD DEAN ,  DAVID BRIAN GRASCO ,  RONALD RIN ROCKHOLD

IPC: G06F15/173 ,  G06F9/48 ,  G06F15/177 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To obtain an interruption processing mechanism equipped with an efficient mechanism for the path specification and transmission of interruption by incorporating a processor which receives external interruption and an interruption source which generate the external interruption. SOLUTION: An NUMA computer system 6 includes plural process nodes 8a to 8n which are interconnected through node interconnection 22. Each memory controller 17 includes an interruption destination unit(IDU) 19. The IDU 19 includes plural registers and logic units which facilitate the path specification and process of interruption. An input/output device 32 and a storage device 34 generate interruptions for a notice of the reception of an input value and a report on error conditions through an interruption request line 35. These external interruptions are collected by interruption source units(ISU) 28a and 28b. The ISU 28 allocates the path of an external interruption to the IDU 19, which passes the external interruption and other interruptions to a local processor 10 through an interruption request line 36 for processing.