公开(公告)号：WO2009061093A2

公开(公告)日：2009-05-14

申请号：PCT/KR2008006336

申请日：2008-10-28

Applicant: IBM ,  IBM KOREA INC ,  PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  GEBARA FADI HIKMAT ,  KAO JERRY CHANG-JUI ,  NOWKA KEVIN JOHN ,  CARPENTER GARY DALE

Inventor： PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  GEBARA FADI HIKMAT ,  KAO JERRY CHANG-JUI ,  NOWKA KEVIN JOHN ,  CARPENTER GARY DALE

IPC: G11C29/00

CPC classification number: G11C7/22 ,  G11C7/12 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaulate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variaton from die-to-die and under varying environments, e.g., voltage and temperature variation.

Abstract translation: 包括具有可编程定时的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。 本地时钟缓冲器可独立调整控制字线和局部位线预充电脉冲的本地时钟的脉冲宽度，以及控制全局位线预充电，延迟和读取数据锁存的延迟时钟的脉冲宽度。 本地时钟和延迟时钟之间的延迟也可以调整。 通过改变本地和延迟时钟信号的脉冲宽度以及时钟间延迟，阵列中每个单元的时序余量可以通过以不同的脉冲宽度和时钟延迟读取和写入单元来评估。 由此产生的评估可用于评估芯片内的时序裕度变化，以及芯片到芯片和变化环境下的变化，例如电压和温度变化。

公开(公告)号：WO2007118770A2

公开(公告)日：2007-10-25

申请号：PCT/EP2007052907

申请日：2007-03-27

Applicant: IBM ,  IBM UK ,  CRANFORD HAYDEN CLAVIE JR ,  GEBARA FADI HIKMAT ,  SCHAUB JEREMY DANIEL

Inventor： CRANFORD HAYDEN CLAVIE JR ,  GEBARA FADI HIKMAT ,  SCHAUB JEREMY DANIEL

IPC: G01R29/26

CPC classification number: G01R31/31709 ,  G01R31/31725

Abstract: A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.

Abstract translation: 用于从时钟信号比较确定抖动和脉冲宽度的方法和装置提供了一种低成本和可生产可集成的机制，用于测量具有未知频率的参考时钟的时钟信号。 测量的时钟信号在参考时钟的转变时被采样，并且采样值根据时基的折叠被收集在直方图中，时基被扫描以检测折叠数据的最小抖动，或者从直接频率获得 分析样本集。 统计分析正确估计周期的直方图以产生脉冲宽度，其是概率密度函数和抖动的峰值之间的差异，其对应于密度函数峰值的宽度。 通过调整用于将样本集合中的数据折叠的时基来校正频率漂移。

公开(公告)号：GB2464126A

公开(公告)日：2010-04-07

申请号：GB0818192

申请日：2008-10-04

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  GEBARA FADI HIKMAT ,  KAO JERY CHANG-JUI ,  KUANG JENTE BENEDICT ,  NOWKA KEVIN JOHN ,  PANG LIANG-TECK

IPC: G11C7/22 ,  G11C11/413 ,  G11C29/00

Abstract: A storage array is provided with a local clock buffer 18 which produces local clock signal LCLK and delayed local clock signal DELLCLK both with adjustable tunings based upon global clock signal GLK. The adjustment of the local clock signals is provided by control signal(s) ADJUST input into the array. The ADJUST control signal(s) comprise at least one, preferably three, value(s) for setting at least a timing of the local clock signal(s). The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaluate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. There is also provided a mechanism and method for evaluating circuit timing internal to the storage array by varying the control value(s) until a point of failure is reached. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.