公开(公告)号：WO2009061093A2

公开(公告)日：2009-05-14

申请号：PCT/KR2008006336

申请日：2008-10-28

Applicant: IBM ,  IBM KOREA INC ,  PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  GEBARA FADI HIKMAT ,  KAO JERRY CHANG-JUI ,  NOWKA KEVIN JOHN ,  CARPENTER GARY DALE

Inventor： PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  GEBARA FADI HIKMAT ,  KAO JERRY CHANG-JUI ,  NOWKA KEVIN JOHN ,  CARPENTER GARY DALE

IPC: G11C29/00

CPC classification number: G11C7/22 ,  G11C7/12 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaulate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variaton from die-to-die and under varying environments, e.g., voltage and temperature variation.

Abstract translation: 包括具有可编程定时的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。 本地时钟缓冲器可独立调整控制字线和局部位线预充电脉冲的本地时钟的脉冲宽度，以及控制全局位线预充电，延迟和读取数据锁存的延迟时钟的脉冲宽度。 本地时钟和延迟时钟之间的延迟也可以调整。 通过改变本地和延迟时钟信号的脉冲宽度以及时钟间延迟，阵列中每个单元的时序余量可以通过以不同的脉冲宽度和时钟延迟读取和写入单元来评估。 由此产生的评估可用于评估芯片内的时序裕度变化，以及芯片到芯片和变化环境下的变化，例如电压和温度变化。

公开(公告)号：WO2010037815A3

公开(公告)日：2010-08-05

申请号：PCT/EP2009062758

申请日：2009-10-01

Applicant: IBM ,  IBM UK ,  PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  CARPENTER GARY DALE ,  NOWKA KEVIN JOHN

Inventor： PANG LIANG-TECK ,  KUANG JENTE BENEDICT ,  CARPENTER GARY DALE ,  NOWKA KEVIN JOHN

IPC: G11C7/22 ,  G11C11/417 ,  G11C11/419

CPC classification number: G11C11/417 ,  G11C7/22 ,  G11C11/419

Abstract: A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random- access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.

Abstract translation: 延迟电路具有在较低电压电平处的固定延迟路径，电平转换器以及在较高电压电平处的可调整延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在用于静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电压电平，并且较高的电压电平是SRAM的电压电平。 这些电压可能随动态电压调整而变化，需要重新校准可调延迟路径。 可以通过逐渐增加SRAM阵列的读取访问时间来校准可调整的延迟路径，直到同时发生的读取操作返回正确的输出为止，或者通过使用复制SRAM路径来模拟随着电压供给的变化而引起的延迟变化。

公开(公告)号：JP2013232275A

公开(公告)日：2013-11-14

申请号：JP2013107770

申请日：2013-05-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： PANG LIANG-TECK ,  JENTE BENEDICT KUANG ,  GARY D CARPENTER ,  KEVIN JOHN NOWKA

IPC: G11C11/417 ,  G06F1/04 ,  G11C11/413 ,  H03K5/135

CPC classification number: G11C11/417 ,  G11C7/22 ,  G11C11/419

Abstract: PROBLEM TO BE SOLVED: To provide a method of operating a memory array such as static random-access memory (SRAM) which uses locally generated clock signals.SOLUTION: A delay circuit has a fixed delay path 12 at a lower voltage level, a level converter 36, and an adjustable delay path 14' at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to a circuit output. In an application for a local clock buffer 30 of a static random-access memory (SRAM) 32, the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns a correct output.

Abstract translation: 要解决的问题：提供一种操作诸如使用本地生成的时钟信号的静态随机存取存储器（SRAM）的存储器阵列的方法。解决方案：延迟电路具有处于较低电压电平的固定延迟路径12， 转换器36和可调延迟路径14'处于较高电压电平。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）32的本地时钟缓冲器30的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取存取时间来校准，直到同时读取操作返回正确的输出。

公开(公告)号：GB2464126A

公开(公告)日：2010-04-07

申请号：GB0818192

申请日：2008-10-04

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  GEBARA FADI HIKMAT ,  KAO JERY CHANG-JUI ,  KUANG JENTE BENEDICT ,  NOWKA KEVIN JOHN ,  PANG LIANG-TECK

IPC: G11C7/22 ,  G11C11/413 ,  G11C29/00

Abstract: A storage array is provided with a local clock buffer 18 which produces local clock signal LCLK and delayed local clock signal DELLCLK both with adjustable tunings based upon global clock signal GLK. The adjustment of the local clock signals is provided by control signal(s) ADJUST input into the array. The ADJUST control signal(s) comprise at least one, preferably three, value(s) for setting at least a timing of the local clock signal(s). The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaluate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. There is also provided a mechanism and method for evaluating circuit timing internal to the storage array by varying the control value(s) until a point of failure is reached. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.