公开(公告)号：CA1155558A

公开(公告)日：1983-10-18

申请号：CA382815

申请日：1981-07-29

Applicant: IBM

Inventor： CHANG WEN H ,  GHEEWALA TUSHAR R ,  HARRIS ERIK P

IPC: H01L27/18 ,  H01L39/02 ,  H01L39/22 ,  H01L39/00

Abstract: MOAT GUARDED JOSEPHSON DEVICES In superconductive circuitry including a super conducting ground plane, a magnetic flux trapping moat is provided which surrounds a superconductive device. The moat is preferably a cut through the superconducting ground plane which extends along a perimeter surrounding the superconducting device, the moat being continuous except for small regions where there is no cut. The small regions serve as current carrying portions to link the ground plane within the moat to the rest of the ground plane outside of the moat. The moat is a flux pinning center so that magnetic flux does not enter the ground plane region located near the superconducting device. In a Josephson circuit, the Josephson tunnel devices are especially sensitive to trapped magnetic flux in the ground plane, and the provision of a moat around each of the devices prevents flux from moving into the ground plane areas near the devices and becoming trapped therein.

公开(公告)号：CA1197290A

公开(公告)日：1985-11-26

申请号：CA433745

申请日：1983-08-03

Applicant: IBM

Inventor： GHEEWALA TUSHAR R ,  KAPLAN STEVEN B

IPC: H03K7/02 ,  G01R13/34 ,  H01L39/22 ,  H03K17/92 ,  H03K19/195

Abstract: SOLITON SAMPLER The invention is an all-soliton sampler for accessing very high speed circuits. A soliton is switched in two parallel branches, one including the device under test and the other including a programmable delay line implemented in soliton devices. The outputs of these two branches are used as controls to a soliton comparator which, in turn, controls a Josephson detector gate. This circuit permits a relatively slow rise time external trigger pulse to initiate an extremely narrow sampling pulse. An object of the invention is to reduce the width of the sampling pulse (which is of order 5ps, set by the inductance and capacitance of the pulse generator) in order to decrease jitter, to obtain the fastest trigger pulse possible without generating appreciable crosstalk. In the soliton sampler according to this invention, extremely narrow test-gate trigger signals and sampling pulses (of width A? 1 ps) are generated simultaneously by an external trigger with a relatively long rise time. The addition of an on-chip programmable delay circuit allows highresolution sampling to be done without appreciable jitter. Problems with crosstalk are alleviated by allowing a long rise time on the external trigger.

公开(公告)号：CA1177911A

公开(公告)日：1984-11-13

申请号：CA393796

申请日：1982-01-08

Applicant: IBM

Inventor： GHEEWALA TUSHAR R

IPC: H03K17/92 ,  G05F3/02 ,  H01L39/22 ,  G05F1/46

Abstract: YO981-018 JOSEPHSON CURRENT REGULATOR A Josephson current regulator circuit is described for regulating the gate current to a Josephson load device. The regulator circuit is located between the source of the gate current and the Josephson load, and is comprised of Josephson devices having a critical current less than the critical current of the Josephson load device. Each of the Josephson regulator devices has at least two states dependent upon the magnitude of the gate current. A resistance is associated with each of the Josephson regulator devices so that, when the state of the Josephson regulator device is changed, resistance is either introduced or removed from the circuit connecting the source and the Josephson load. This adjusts the magnitude of the gate current and maintains within a specified range the ratio of the gate current to the critical current of the Josephson load device.

公开(公告)号：CA1228170A

公开(公告)日：1987-10-13

申请号：CA482001

申请日：1985-05-21

Applicant: IBM

Inventor： KRONSTADT ERIC P ,  GHEEWALA TUSHAR R ,  GANDHI SHARAD P

IPC: G06F12/08 ,  G06F9/38

Abstract: ARCHITECTURE FOR SMALL INSTRUCTION CACHES A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), a valid entries table (16) and an instruction table (18). whenever a branch is taken, some of the bits in the untranslated part of the address of the target instruction , i.e. the instruction being branched to, are used to address a line of the branch target table (10). In parallel with address translation, all entries of the branch target table line are accessed, and the translated address is compared to the target address table (12) entry on that line. If the target address table entry matches the target address, the instruction prefetch unit (32) fetches the instruction addressed by the next fetch address table (14) entry for the given line and the line of instructions associated with the branch address table entry is read into an instruction queue (38) having a length set by the valid entry table (16) entry which indicates how many of these instructions are valid. Otherwise, the instruction prefetch unit (32) fetches the target and subsequent instructions as it would if there were no branch target table, and the target address table entry is set to the real address of the target instruction. The next fetch address table (14) is updated so that it always contains the address of the instruction which follows the last valid instruction in the line, and the valid entries table (16) is updated so that it always counts the number of valid instructions in the line.

公开(公告)号：CA1157151A

公开(公告)日：1983-11-15

申请号：CA373894

申请日：1981-03-26

Applicant: IBM

Inventor： GHEEWALA TUSHAR R

IPC: G11C11/44 ,  H01L39/22 ,  H03K3/38 ,  H03K17/92 ,  H03K19/195

Abstract: SUPERCONDUCTIVE LATCH CIRCUIT This superconductive latch circuit uses superconductive switching devices and can be powered by the same phase of AC power used to power other circuits with which the latch is used. The latch is comprised of a storage loop including a superconductive switch and an inductor. It is also comprised of another superconductive switch through which an AC gate current can flow and whose state determines whether or not the AC current is delivered to the superconductive storage loop. Information is stored in the loop as the presence and absence of a circulating current of either polarity. In a variation of this latch, an output of the sense circuit which detects the state of the storage loop if fed back as a control signal to the superconductive switch in the storage loop and also as one input to an AND gate to which a SET signal is also applied. AC power is switched to the storage loop when both inputs to the AND circuit are simultaneously present. In another variation, the signal which is fed back from the sense circuit is an input to an OR gate, whose output is the control signal to the switch in the storage loop. This latch reliably holds data when the AC power diminishes to zero, and also when the AC power changes polarity. Y0980042

公开(公告)号：CA1089540A

公开(公告)日：1980-11-11

申请号：CA295188

申请日：1978-01-18

Applicant: IBM

Inventor： GHEEWALA TUSHAR R

IPC: H01L27/18 ,  H01L39/22 ,  H03K17/92 ,  H03K19/195

Abstract: TWO-PORT CURRENT INJECTION INTERFEROMETER AMPLIFIERS AND LOGIC CIRCUITS Josephson junction interferometers having nonlinear switching or threshold characteristics are disclosed. The nonlinear threshold characteristic is achieved in a preferred manner by applying an injection current to the interferometer at a point on the interferometer which is different from where its gate current is normally applied. The resulting nonlinearity provides for high amplification. The nonlinear switching characteristic may also be achieved by applying an injection current to the same point on the interferometer where_the gate current is normally applied. However, a portion of the thus-applied injection current is electromagnetically coupled to the interferometer inductance to achieve the desired nonlinear switching characteristic. Parameters such as the injection current, the gate current, physical point of application of the injection current to the interferometer, junction currents and the inductance of the interferometer may be changed to tailor the threshold characteristic to provide a desired nonlinearity. Logic circuits such as AND, OR and INHIBIT circuits in addition to the basic amplifier circuit are also disclosed.

公开(公告)号：FR2396467A1

公开(公告)日：1979-01-26

申请号：FR7805800

申请日：1978-02-23

Applicant: IBM

Inventor： GHEEWALA TUSHAR R

IPC: H01L27/18 ,  H01L39/22 ,  H03K17/92 ,  H03K19/195

Abstract: TWO-PORT CURRENT INJECTION INTERFEROMETER AMPLIFIERS AND LOGIC CIRCUITS Josephson junction interferometers having nonlinear switching or threshold characteristics are disclosed. The nonlinear threshold characteristic is achieved in a preferred manner by applying an injection current to the interferometer at a point on the interferometer which is different from where its gate current is normally applied. The resulting nonlinearity provides for high amplification. The nonlinear switching characteristic may also be achieved by applying an injection current to the same point on the interferometer where_the gate current is normally applied. However, a portion of the thus-applied injection current is electromagnetically coupled to the interferometer inductance to achieve the desired nonlinear switching characteristic. Parameters such as the injection current, the gate current, physical point of application of the injection current to the interferometer, junction currents and the inductance of the interferometer may be changed to tailor the threshold characteristic to provide a desired nonlinearity. Logic circuits such as AND, OR and INHIBIT circuits in addition to the basic amplifier circuit are also disclosed.