公开(公告)号：JP2008171426A

公开(公告)日：2008-07-24

申请号：JP2008000839

申请日：2008-01-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RICHARD NICHOLAS ,  DRERUP BERNARD CHARLES ,  JYOTI GUPTA ,  GIORA BIRAN ,  TORRE LUIS E DE LA

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: PROBLEM TO BE SOLVED: To provide a DMA device prefetching descriptors into a descriptor prefetch buffer.
SOLUTION: The size of the descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, sequential descriptors are prefetched, and descriptors contrary to them are discarded. A DMA engine 412 keeps the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. A bus engine 414 fetches these descriptors from a system memory 430 and writes them in the prefetch buffer. The DMA engine may use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer supports when there is any space in the descriptor prefetch buffer.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供DMA设备将描述符预取到描述符预取缓冲器中。 解决方案：描述符预取缓冲区的大小在给定的延迟环境中保存适当数量的描述符。 为了支持描述符的链表，序列描述符被预取，并且与之相反的描述符被丢弃。 DMA引擎412通过每个事务请求多个描述符尽可能地保持描述符预取缓冲器满。 总线引擎414从系统存储器430中取出这些描述符，并将它们写入预取缓冲器。 DMA引擎可以使用积极的预取，其中当在描述符预取缓冲器中存在任何空间时，总线引擎请求缓冲器支持的最大数量的描述符。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：GB2581693B

公开(公告)日：2022-01-12

申请号：GB202006469

申请日：2018-08-02

Applicant: IBM

Inventor： GIORA BIRAN ,  PREETHAM LOBO ,  TOBIAS WEBEL ,  ALPER BUYUKTOSUNOGLU ,  CHRISTOS VEZYRTZIS ,  RAMON BERTRAN MONFORT ,  PIERCE I-JEN CHUANG ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: G06F1/30 ,  G06F1/28 ,  G06F1/32 ,  G06F9/38

Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

公开(公告)号：GB2581693A

公开(公告)日：2020-08-26

申请号：GB202006469

申请日：2018-08-02

Applicant: IBM

Inventor： GIORA BIRAN ,  PREETHAM LOBO ,  TOBIAS WEBEL ,  ALPER BUYUKTOSUNOGLU ,  CHRISTOS VEZYRTZIS ,  RAMON BERTRAN MONFORT ,  PIERCE I-JEN CHUANG ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: G06F1/30 ,  G06F1/28 ,  G06F1/32 ,  G06F9/38

Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.