公开(公告)号：GB2632957A

公开(公告)日：2025-02-26

申请号：GB202416053

申请日：2023-01-17

Applicant: IBM

Inventor： ADAM COLLURA ,  MICHAEL ROMAIN ,  WILLIAM HUOTT ,  PAWEL OWCZARCZYK ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  CHUNG-LUNG SHUM ,  ALPER BUYUKTOSUNOGLU ,  TOBIAS WEBEL ,  MICHAEL CADIGAN JR ,  PAUL LOGSDON ,  SEAN CAREY ,  KARL ANDERSON ,  MARK CICHANOWSKI ,  STEFAN PAYER

IPC: H02H9/04 ,  G05F1/571 ,  H02H3/20

Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. The method includes detecting a region, such as an individual processor, of a processor chip exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life. The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltage spikes back to within some pre-specified range. The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

公开(公告)号：GB2605242A

公开(公告)日：2022-09-28

申请号：GB202117765

申请日：2021-12-09

Applicant: IBM

Inventor： TONG CHEN ,  RICHARD HAROLD BOIVIE ,  ALPER BUYUKTOSUNOGLU

IPC: G06F9/30

Abstract: A method, system and apparatus for providing bound information accesses in buffer protection, including providing one-to-one mapping between a general-purpose register and bound information in a BI (bound information) register, saving loaded bound information in the BI register for future use, providing integrity of the bound information in the BI register that is maintained along program execution, and providing a pro-active load of the bound information with one-bit extra control on load instruction of the BI register. A compiler may determine candidate loads for the pro-active load of the bound information. The method may comprise reducing load request for bound information or hiding load latency or selecting profitable cases with static program analysis.

公开(公告)号：GB2581693B

公开(公告)日：2022-01-12

申请号：GB202006469

申请日：2018-08-02

Applicant: IBM

Inventor： GIORA BIRAN ,  PREETHAM LOBO ,  TOBIAS WEBEL ,  ALPER BUYUKTOSUNOGLU ,  CHRISTOS VEZYRTZIS ,  RAMON BERTRAN MONFORT ,  PIERCE I-JEN CHUANG ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: G06F1/30 ,  G06F1/28 ,  G06F1/32 ,  G06F9/38

Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

公开(公告)号：GB2628249B

公开(公告)日：2025-02-12

申请号：GB202408070

申请日：2022-10-08

Applicant: IBM

Inventor： AARON DINGLER ,  MOHIT KARVE ,  ALPER BUYUKTOSUNOGLU

IPC: G06F12/121 ,  G06F12/08

Abstract: A method, system, and computer program product for augmenting cache replacement operations are provided. The method identifies a set of cache lines within a first cache level of a multilevel cache. A first candidate cache line is identified based on a first replacement scheme of the first cache level. A second candidate cache line is identified based on the first replacement scheme of the first cache level. A replacement cache line is selected for replacement in the first cache level. The replacement cache line is selected from the first candidate cache line and the second candidate cache line and based on the first replacement scheme of the first cache level and a second replacement scheme of a second cache level. The method removes the replacement cache line from the first cache level.

公开(公告)号：GB2605678A

公开(公告)日：2022-10-12

申请号：GB202117483

申请日：2021-12-03

Applicant: IBM

Inventor： TONG CHEN ,  ALPER BUYUKTOSUNOGLU ,  RICHARD HAROLD BOIVIE

IPC: G06F9/30 ,  G06F12/14

Abstract: A method, system and apparatus for protecting against out-of-bounds references, including storing an address of a buffer in a general register and storing bounds information (BI) for the buffer in a bounds information register, and when a content of the general register is used as an address in a load or store operation, using a content of the bounds information register to determine if the load or store is out of bounds.

公开(公告)号：GB2581693A

公开(公告)日：2020-08-26

申请号：GB202006469

申请日：2018-08-02

Applicant: IBM

Inventor： GIORA BIRAN ,  PREETHAM LOBO ,  TOBIAS WEBEL ,  ALPER BUYUKTOSUNOGLU ,  CHRISTOS VEZYRTZIS ,  RAMON BERTRAN MONFORT ,  PIERCE I-JEN CHUANG ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: G06F1/30 ,  G06F1/28 ,  G06F1/32 ,  G06F9/38

Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

公开(公告)号：GB2513787B

公开(公告)日：2016-11-23

申请号：GB201414719

申请日：2013-01-24

Applicant: IBM

Inventor： BRIAN ROBERT PRASKY ,  ALPER BUYUKTOSUNOGLU ,  VIJAYALAKSHMI SRINIVASAN

IPC: G06F9/38

公开(公告)号：GB2604201A

公开(公告)日：2022-08-31

申请号：GB202113829

申请日：2021-09-28

Applicant: IBM

Inventor： RICHARD HAROLD BOIVIE ,  TONG CHEN ,  ALPER BUYUKTOSUNOGLU ,  GURURAJ SAILESHWAR

IPC: G06F12/02 ,  G06F12/14

Abstract: Techniques facilitating hardware-based memory-error mitigation for heap-objects. In one example, a system can comprise a process that executes computer executable components stored in a non-transitory computer readable medium. The computer executable components comprise: an entry component; and a re-purpose component. The entry component can allocate an entry in a table to store bounds-information when an object is allocated in memory. The re-purpose component can re-purpose unused bits of an object address to store an index to the table entry.

公开(公告)号：GB2579316B

公开(公告)日：2021-09-29

申请号：GB202002342

申请日：2018-07-27

Applicant: IBM

Inventor： CHRISTOS VEZYRTZIS ,  PIERCE I-JEN CHUANG ,  ALPER BUYUKTOSUNOGLU ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: H03K19/003 ,  G06F1/30

Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.

公开(公告)号：GB2579316A

公开(公告)日：2020-06-17

申请号：GB202002342

申请日：2018-07-27

Applicant: IBM

Inventor： CHRISTOS VEZYRTZIS ,  PIERCE I-JEN CHUANG ,  ALPER BUYUKTOSUNOGLU ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: G06F1/32

Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.