公开(公告)号：GB2581693B

公开(公告)日：2022-01-12

申请号：GB202006469

申请日：2018-08-02

Applicant: IBM

Inventor： GIORA BIRAN ,  PREETHAM LOBO ,  TOBIAS WEBEL ,  ALPER BUYUKTOSUNOGLU ,  CHRISTOS VEZYRTZIS ,  RAMON BERTRAN MONFORT ,  PIERCE I-JEN CHUANG ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: G06F1/30 ,  G06F1/28 ,  G06F1/32 ,  G06F9/38

Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

公开(公告)号：GB2577234B

公开(公告)日：2020-08-05

申请号：GB202000045

申请日：2018-06-07

Applicant: IBM

Inventor： CHRISTOS VEZYRTZIS ,  PAWEL OWCZARCZYK

IPC: H03K5/15 ,  G01R31/317 ,  H03K3/037 ,  H03K5/19

公开(公告)号：GB2579316B

公开(公告)日：2021-09-29

申请号：GB202002342

申请日：2018-07-27

Applicant: IBM

Inventor： CHRISTOS VEZYRTZIS ,  PIERCE I-JEN CHUANG ,  ALPER BUYUKTOSUNOGLU ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: H03K19/003 ,  G06F1/30

Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.

公开(公告)号：GB2579316A

公开(公告)日：2020-06-17

申请号：GB202002342

申请日：2018-07-27

Applicant: IBM

Inventor： CHRISTOS VEZYRTZIS ,  PIERCE I-JEN CHUANG ,  ALPER BUYUKTOSUNOGLU ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: G06F1/32

Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.

公开(公告)号：GB2581693A

公开(公告)日：2020-08-26

申请号：GB202006469

申请日：2018-08-02

Applicant: IBM

Inventor： GIORA BIRAN ,  PREETHAM LOBO ,  TOBIAS WEBEL ,  ALPER BUYUKTOSUNOGLU ,  CHRISTOS VEZYRTZIS ,  RAMON BERTRAN MONFORT ,  PIERCE I-JEN CHUANG ,  PHILLIP JOHN RESTLE ,  PRADIP BOSE

IPC: G06F1/30 ,  G06F1/28 ,  G06F1/32 ,  G06F9/38

Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

公开(公告)号：GB2577234A

公开(公告)日：2020-03-18

申请号：GB202000045

申请日：2018-06-07

Applicant: IBM

Inventor： CHRISTOS VEZYRTZIS ,  PAWEL OWCZARCZYK

IPC: H03K5/15 ,  G01R31/317 ,  H03K3/037 ,  H03K5/19

Abstract: A system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.