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    3.
    发明专利
    未知

    公开(公告)号：DE1965565A1

    公开(公告)日：1970-07-16

    申请号：DE1965565

    申请日：1969-12-30

    Applicant: IBM

    Inventor： BEAUDOUIN PIERRE ,  GLANG REINHARD ,  RISEMAN JACOB

    IPC: H01L29/43 ,  H01L21/00 ,  H01L21/28 ,  H01L23/485 ,  H01L23/522 ,  H01L5/06

    Abstract: 1,269,130. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 17 Nov., 1969 [3 Jan., 1969], No. 56104/69. Heading H1K. Ohmic contact to a semi-conductor body is made within an aperture in a surface insulating layer by a layer of silicon monoxide-chromium cermet overcoated with a metal layer. A silicon or germanium body may be provided with an apertured coating of a silicon oxide, nitride, or oxide-nitride, or of a silicate glass. The cermet is applied to the entire surface at a substrate temperature of 100-500‹C. by flash evaporation of a sintered mixture of its two components or by coevaporation of the two components from separate sources. The chromium content of the cermet may be 50-90 atomic per cent. Without breaking vacuum, a layer of copper, silver or gold is applied and may be followed by a flashed layer of chromium or titanium. After selective etching to leave a contact and track pattern (resistors are formed in the pattern by the removal of the metallic layers to leave the cermet only), the system is baked for 1 hour at 300- 500‹ C. to effect diffusion of cermet components into the semi-conductor. A single- or multiplelayer insulation is applied and apertures formed at terminal areas. Further interconnection levels may be provided.

    4.
    发明专利
    未知

    公开(公告)号：DE2639465A1

    公开(公告)日：1977-03-31

    申请号：DE2639465

    申请日：1976-09-02

    Applicant: IBM

    Inventor： GLANG REINHARD ,  RAIDER STANLEY IRWIN

    IPC: H01L29/73 ,  H01L21/22 ,  H01L21/283 ,  H01L21/3115 ,  H01L21/331 ,  H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L29/78 ,  H01L27/04

    Abstract: Surface leakage paths on bipolar and FET transistors may be significantly reduced by the presence of a fixed charge in an insulating layer adhered to a semiconductor wafer. The fixed charge consists of ions which are introduced into the insulating layer after all high-temperature process treatments have been performed on the wafer. The ions are introduced into the insulating layer by (1) immersing the wafer in a solution of a suitable metal salt; (2) sandwiching the wafers between carefully cleaned non-immersed wafers and (3) driving the ions to the insulating layer-wafer interface by heating the wafer stacks in a furnace at a preselected temperature. The effective charge level embedded in the insulating layer is sufficient to protect against inversion of the wafer surface due to conductors on the insulating layer having negative potentials exceeding 10 volts and overlying the stored-charge area.

    5.
    发明专利
    未知

    公开(公告)号：DE3850847T2

    公开(公告)日：1995-03-09

    申请号：DE3850847

    申请日：1988-10-11

    Applicant: IBM

    Inventor： GLANG REINHARD ,  KU SAN MEI

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732 ,  H01L21/82 ,  H01L21/225

    Abstract: A semiconductor process for fabricating bipolar devices of one type and extendible to include bipolar devices of a second type in the same epi-layer. The process protects selected surfaces of the epi-layer against deleterious processes associated with the formation of future emitter/contact regions for the devices. Subsequently, such emitter/contact regions are formed beneath such protected surfaces and contribute to enhanced device performance. The process also provides improved planarization of an insulating layer on the epi-layer by chemical-mechanical polishing. The planarization in conjunction with a mask formed in the insulating layer facilitates the formation of self-aligned emitter/base regions to appropriate thicknesses for high performance devices.

    6.
    发明专利
    未知

    公开(公告)号：DE3850847D1

    公开(公告)日：1994-09-01

    申请号：DE3850847

    申请日：1988-10-11

    Applicant: IBM

    Inventor： GLANG REINHARD ,  KU SAN MEI

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732 ,  H01L21/82 ,  H01L21/225

    Abstract: A semiconductor process for fabricating bipolar devices of one type and extendible to include bipolar devices of a second type in the same epi-layer. The process protects selected surfaces of the epi-layer against deleterious processes associated with the formation of future emitter/contact regions for the devices. Subsequently, such emitter/contact regions are formed beneath such protected surfaces and contribute to enhanced device performance. The process also provides improved planarization of an insulating layer on the epi-layer by chemical-mechanical polishing. The planarization in conjunction with a mask formed in the insulating layer facilitates the formation of self-aligned emitter/base regions to appropriate thicknesses for high performance devices.

    7.
    发明专利
    未知

    公开(公告)号：FR2325196A1

    公开(公告)日：1977-04-15

    申请号：FR7623078

    申请日：1976-07-20

    Applicant: IBM

    Inventor： GLANG REINHARD ,  RAIDER STANLEY I

    IPC: H01L29/73 ,  H01L21/22 ,  H01L21/283 ,  H01L21/3115 ,  H01L21/331 ,  H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L29/78 ,  H01L29/36 ,  H01L21/322

    Abstract: Surface leakage paths on bipolar and FET transistors may be significantly reduced by the presence of a fixed charge in an insulating layer adhered to a semiconductor wafer. The fixed charge consists of ions which are introduced into the insulating layer after all high-temperature process treatments have been performed on the wafer. The ions are introduced into the insulating layer by (1) immersing the wafer in a solution of a suitable metal salt; (2) sandwiching the wafers between carefully cleaned non-immersed wafers and (3) driving the ions to the insulating layer-wafer interface by heating the wafer stacks in a furnace at a preselected temperature. The effective charge level embedded in the insulating layer is sufficient to protect against inversion of the wafer surface due to conductors on the insulating layer having negative potentials exceeding 10 volts and overlying the stored-charge area.

    9.
    发明专利
    未知

    公开(公告)号：DE3689032T2

    公开(公告)日：1994-04-14

    申请号：DE3689032

    申请日：1986-10-21

    Applicant: IBM

    Inventor： HWANG BAO TAI ,  ORR-ARIENZO WENDY ANN ,  GLANG REINHARD

    IPC: H01L21/306 ,  H01L21/308

    Abstract: The present invention provides an etchant composition and method for the resistivity specific etching of doped silicon films which overlie intrinsic or lightly doped crystal regions.The etchant comprises hydrofluoric acid, nitric acid, and acetic acid, the molecular ratio of nitric acid to hydrofluoric acid being greater than 2,0 and the mole percentage of nitric acid being greater than 14 mole %.The etchant leaves no silicon residue and provides for controlled etching with an etch stop at the lightly doped or intrinsic region.The method comprises the steps of:providing an etch mask overlying the silicon layer;immersing the doped silicon on the crystal surface in the etchant; andetching portions of the doped silicon layer exposed through the mask in the solution until the exposed doped silicon is removed and the underlying surface is clear and specular.

    10.
    发明专利
    未知

    公开(公告)号：DE3689032D1

    公开(公告)日：1993-10-21

    申请号：DE3689032

    申请日：1986-10-21

    Applicant: IBM

    Inventor： HWANG BAO TAI ,  ORR-ARIENZO WENDY ANN ,  GLANG REINHARD

    IPC: H01L21/306 ,  H01L21/308

    Abstract: The present invention provides an etchant composition and method for the resistivity specific etching of doped silicon films which overlie intrinsic or lightly doped crystal regions.The etchant comprises hydrofluoric acid, nitric acid, and acetic acid, the molecular ratio of nitric acid to hydrofluoric acid being greater than 2,0 and the mole percentage of nitric acid being greater than 14 mole %.The etchant leaves no silicon residue and provides for controlled etching with an etch stop at the lightly doped or intrinsic region.The method comprises the steps of:providing an etch mask overlying the silicon layer;immersing the doped silicon on the crystal surface in the etchant; andetching portions of the doped silicon layer exposed through the mask in the solution until the exposed doped silicon is removed and the underlying surface is clear and specular.

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