公开(公告)号：JP2003188914A

公开(公告)日：2003-07-04

申请号：JP2002318107

申请日：2002-10-31

Applicant: IBM

Inventor： GOETZINGER WILLIAM JOHN ,  HANDLOGTEN GLEN ,  MIKOS JAMES F ,  NORGAARD DAVID ALAN

IPC: H04L12/54 ,  H04L12/851 ,  H04L12/863 ,  H04L12/935 ,  H04L12/937 ,  H04L13/08 ,  H04L29/04 ,  H04L29/06 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide a device and method by which the number of output ports to be serviced by scheduling queues can be increased without reducing the effects of the scheduling queues or increasing the resources consumed by physical array spaces used for the scheduling queues. SOLUTION: Data communication equipment includes a plurality of output ports and a scheduler which assigns priority order to outbound data frames. The scheduler includes one or a plurality of scheduling queues. Each scheduling queue expresses the serviced order of data flows. At least one scheduling queue has a plurality of output ports assigned to the queue. Namely, the scheduling queue is commonly used by two or more output ports. COPYRIGHT: (C)2003,JPO

公开(公告)号：AU2002251004A1

公开(公告)日：2002-09-19

申请号：AU2002251004

申请日：2002-01-31

Applicant: IBM

Inventor： HANDLOGTEN GLEN HOWARD ,  CALVIGNAC JEAN LOUIS ,  LOGAN JOSEPH FRANKLIN ,  VERPLANKEN FABRICE ,  GOETZINGER WILLIAM JOHN ,  MIKOS JAMES FRANCIS ,  NORGAARD DAVID ALAN ,  HEDDES MARCO C

IPC: H04L12/56 ,  H04L12/44 ,  H04Q11/04

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.