公开(公告)号：AU2002251004A1

公开(公告)日：2002-09-19

申请号：AU2002251004

申请日：2002-01-31

Applicant: IBM

Inventor： HANDLOGTEN GLEN HOWARD ,  CALVIGNAC JEAN LOUIS ,  LOGAN JOSEPH FRANKLIN ,  VERPLANKEN FABRICE ,  GOETZINGER WILLIAM JOHN ,  MIKOS JAMES FRANCIS ,  NORGAARD DAVID ALAN ,  HEDDES MARCO C

IPC: H04L12/56 ,  H04L12/44 ,  H04Q11/04

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.