公开(公告)号：JP2000347859A

公开(公告)日：2000-12-15

申请号：JP2000126367

申请日：2000-04-26

Applicant: IBM

Inventor： HELLER THOMAS J JR ,  BOYD WILLIAM TODD

IPC: G06F12/08 ,  G06F9/38 ,  G06F15/16 ,  G06F15/80

Abstract: PROBLEM TO BE SOLVED: To reduce the disadvantage of a finite cache and to improve system performance by processing an inference process through an inference engine processing element(PE) and improving the disadvantage of the finite cache detected by a conventional PE. SOLUTION: First PE μm PCore 200, 200' and 200" process the instructions of a successive instruction stream in proper order and control an architecture state. The processing of successive instruction stream is performed while using the first PE μm PCore 200, 200' and 200" for transferring the change in the architecture state of a computer system to second PE SFE 202, 202' and 202". When it is advantageous to make the second PE such as SFE 202 start the continuous processing of the same successive instruction stream at any arbitrary time point during the processing of successive instruction stream due to the first PE such as μm PCore 200, however, the second PE SFE 200 restores the transferred state and processes the successive instruction stream.

公开(公告)号：JP2001147903A

公开(公告)日：2001-05-29

申请号：JP2000278528

申请日：2000-09-13

Applicant: IBM

Inventor： MICHAEL IGNATOSKI ,  HELLER THOMAS J JR ,  GOLDRIAN GOTTFRIED

IPC: G06F12/06 ,  G06F12/08 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a novel structure for a highly scalable high-performance shared memory computer system having simple production possibility. SOLUTION: The intra-node bus mechanism of a peculiar type connects respective system cells in each of nodes to the other respective cells inside the same node. An inter-node bus can be shared by plural nodes. Even when all the memory subsets inside all the cells of the shared memory system can be accessed by all processors, bus competition to occur inside a shared memory is remarkably reduced. A node directory automatically manages the coherence of all data to be changed inside all processor caches in the computer system and provides data coherence over all the nodes in the computer system.

公开(公告)号：JP2005018772A

公开(公告)日：2005-01-20

申请号：JP2004185622

申请日：2004-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HELLER THOMAS J JR

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/14 ,  G06F13/00 ,  G06F13/28 ,  G06F15/16 ,  G06F15/177

CPC classification number: G06F12/0831 ,  G06F12/0804 ,  G06F2212/1024 ,  G06F2212/1048

Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor computer system comprising a plurality of coherency regions and software migration across coherency regions without cache purges. SOLUTION: By using an active coherency region information table 14 relating to each processor 10', it is determined when conventional technology of cache situation transition is executed. A supervisor program initializes the table relating to each processor 10'. A table entry is created every coherency region which the supervisor program is going to use on the processor 10'. A unique coherency region ID is assigned to each coherency region, and the supervisor program can associate the ID to all the software process accessing to memory addresses included in the coherency regions. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供包括多个相关性区域的多处理器计算机系统和跨越相干性区域的软件迁移而不进行高速缓存清除。 解决方案：通过使用与每个处理器10'相关的主动一致性区域信息表14，确定何时执行高速缓存状态转换的常规技术。 主管程序初始化与每个处理器10'有关的表格。 在管理程序将要在处理器10'上使用的每个相关性区域中创建一个表条目。 将唯一的一致性区域ID分配给每个相关性区域，并且管理程序可以将ID与所有软件进程相关联，以访问包含在相干区域中的存储器地址。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH11272482A

公开(公告)日：1999-10-08

申请号：JP597399

申请日：1999-01-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： HELLER THOMAS J JR ,  BOYD WILLIAM TODD

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/46 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To reduce the disadvantage of a finite cache and to improve system performance by changing a whole architecture state only in a first or second processing element.
SOLUTION: When it becomes advantageous that the continuous processing of a sequential instruction stream is started by a second processing element 202 at arbitrary time during the processing of the sequential instruction stream by a first processing element 200, the second processing element restores a transferred state and the second processing element processes the sequential instruction stream. Thus, the continuous processing of the same sequential instruction stream is started. Then, the second processing element transfers the change of the architecture state of a computer system which the first processing element requests to the first processing element. Only the first or the second processing element can change the whole architecture state of the computer system decided by the combination of the states of the first and second processing elements.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：为了减少有限缓存的缺点，并且仅通过在第一或第二处理元件中改变整个架构状态来提高系统性能。 解决方案：当在第一处理单元200处理顺序指令流期间的任意时刻连续处理顺序指令流是有利的时候，第二处理单元恢复转移状态， 第二处理元件处理顺序指令流。 因此，开始连续处理相同的顺序指令流。 然后，第二处理单元将第一处理单元要求的计算机系统的体系结构状态的变更传递给第一处理单元。 只有第一或第二处理元件可以改变由第一和第二处理元件的状态的组合决定的计算机系统的整体架构状态。

公开(公告)号：SG77216A1

公开(公告)日：2000-12-19

申请号：SG1999000119

申请日：1999-01-20

Applicant: IBM

Inventor： HELLER THOMAS J JR ,  BOYD WILLIAM TODD

IPC: G06F9/38

Abstract: A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first and a second processing element, each of said processing elements having its own state determined by a setting of its own general purpose and control registers. When at any point in the processing of said sequential stream of instructions by said first processing element it becomes beneficial to have said second processing element begin continued processing of the same sequential instruction stream then the first and second processing elements process the sequential stream of instructions and may be executing the very same instruction but only one of said processing elements is permitted to change the overall architectural state of said computer system which is determined by a combination of the states of said first and second processing elements. The second processor will have more pipeline stages than the first in order processor to feed the first processor and reduce the finite cache penalty and increase performance. The processing and storage of results of the second processor does not change the architectural state of the computer system. Results are stored in its gprs or its personal storage buffer. Resynchronization of states with a coprocessor occurs upon an invalid op, a stall or a computed specific benefit to processing with the coprocessor as a speculative coprocessor. In an alternative embodiment the foregoing process is generalized for both processors allowing processors to forward and store architectural state changes for future use as required by the other processor when at a later time the processor which is permitted to change the overall architectural state of said computer system is changed.