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    Method for measuring resistivity
    1.
    发明授权
    Method for measuring resistivity 失效
    测量电阻率的方法

    公开(公告)号：US3676775A

    公开(公告)日：1972-07-11

    申请号：US3676775D

    申请日：1971-05-07

    Applicant: IBM

    Inventor： DUPNOCK ANDREW ,  GOREY EDWARD F ,  KEENAN WILLIAM A

    IPC: G01N27/04 ,  G01R31/26 ,  G01R27/14

    CPC classification number: G01R31/2637 ,  G01N27/041

    Abstract: The method for measuring the bulk resistivity of an epitaxial semiconductor layer on a monocrystalline semiconductor base with a 4-point probe apparatus wherein the base has at least two high conductivity diffused regions, positioning two current probes directly over two separate diffused regions in contact with the surface of the epitaxial layer, placing two spaced voltage probes in contact with the epitaxial layer in a generally intermediate position relative to the current probes, inducing a current through the current probes and measuring the voltage drop between the voltage probes, calculating the bulk resistivity in accordance with the expression:

    Abstract translation: 用4点探针装置测量单晶半导体基底上的外延半导体层的体电阻率的方法，其中基底具有至少两个高电导率扩散区域，将两个电流探针直接放置在与 外延层的表面，将两个间隔开的电压探针与外延层接触在相对于电流探针的大致中间位置，引起电流通过电流探针并测量电压探针之间的电压降，计算体电阻率 按照表达式：

    Spreading resistance method and apparatus for determining the resistivity of a material
    4.
    发明授权
    Spreading resistance method and apparatus for determining the resistivity of a material 失效
    用于确定材料电阻率的扩展电阻方法和装置

    公开(公告)号：US3590372A

    公开(公告)日：1971-06-29

    申请号：US3590372D

    申请日：1968-12-26

    Applicant: IBM

    Inventor： DESANTIS DOMINIC P ,  DESSAUER RALPH G ,  GOREY EDWARD F ,  POPONIAK MICHAEL R ,  SCHNEIDER CHRISTIAN P ,  SCHUMANN PAUL A JR

    IPC: G01R27/00 ,  G01N27/04 ,  G01R1/067 ,  G01R31/28 ,  H01L21/66 ,  G01R27/14

    CPC classification number: G01R31/2831 ,  G01N27/041 ,  G01R1/06705

    Abstract: A three-point probe is employed to determine the spreading resistance of a material with the spreading resistance probe, which is common to both the current source and a voltage measuring means, being moved into engagement with the material after the other two probes are in engagement with the material. The velocity with which each of the probes engages the material is controlled and is variable. To ascertain that a good contact has been made by the spreading resistance probe and the magnitude of the current flowing through the material from the current source, the voltage measuring means is connected across resistance means in the wire from the current source to the spreading resistance probe and current is directed through the resistance means in opposite directions by flowing through the material between the spreading resistance probe and one of the other two probes. After the magnitude of the current has been determined, the voltage measuring means is connected to the spreading resistance probe adjacent its contact to the material and to the other of the two probes, which is not connected to the current source, to determine the voltage drop through the material due to current from the current source flowing in opposite directions through the material. The amount of difference between the two voltage readings on the specimen indicates if good contact is achieved.

    ION IMPLANTED SEMICONDUCTOR STRUCTURES
    6.
    发明专利
    ION IMPLANTED SEMICONDUCTOR STRUCTURES 未知

    公开(公告)号：CA981372A

    公开(公告)日：1976-01-06

    申请号：CA145126

    申请日：1972-06-20

    Applicant: IBM

    Inventor： BRACK KARL ,  GOREY EDWARD F ,  SCHWUTTKE GUENTER H

    IPC: H01L27/00 ,  H01L21/02 ,  H01L21/265 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

    Abstract: 1376526 Isolation in semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 1 Aug 1972 [6 Oct 1971] 35772/72 Heading H1K An area to form an isolated pocket in the semi-conductor body of an integrated circuit (or of a discrete device), is exposed via an apertured mask of molybdenum, tungsten, platinum, gold, silver, silicon dioxide, or silicon nitride to a beam of ions of the semiconductor itself. A discrete implanted layer is formed at some distance below the surface and has an amorphous form of very high resistivity. The body is remasked to expose only the area where sidewalls are needed and implantation is then continued at the previously used ion energy until amorphous sidewalls are formed which reach the surface. The semi-conductors quoted are silicon and germanium and the structures formed may be anealed for one hour at 550‹ or 400‹ C. respectively without alteration of the resistivity of the amorphous material.

    IMPACT SOUND STRESSING FOR SEMICONDUCTORS
    8.
    发明专利
    IMPACT SOUND STRESSING FOR SEMICONDUCTORS 未知

    公开(公告)号：CA1068009A

    公开(公告)日：1979-12-11

    申请号：CA249502

    申请日：1976-04-02

    Applicant: IBM

    Inventor： GOREY EDWARD F ,  SCHWUTTKE GUENTER H

    IPC: G01N3/32 ,  H01L21/304 ,  H01L21/66

    Abstract: Apparatus for acoustical stressing of semiconductor wafers is disclosed, utilizing a number of small tungsten balls which are bounced on the surface of the wafer to be stressed. The movement of the tungsten balls is effectuated by clamping a wafer at one end of a conduit, the other end being attached to a high intensity loudspeaker The loudspeaker is driven at resonant frequency of the clamped wafer and accordingly the tungsten balls bounce on the surface. This impact creates micro-cracks on the surface of the wafer and number and depth of these cracks can be controlled by power input and the number of tungsten balls utilized. Controlled stressing can thereby be accomplished both in terms of density of micro-cracks and location on the wafer. Impact sound stressing finds utilization in the study of semiconductor surfaces to determine effects of dislocations and micro-splite and in the evaluation of wafer polishing techniques. Structural changes in the original defect pattern due to oxidation can be studied ant a cause and effect relationship between damage and oxidation established. The study of surface characteristics affecting many semi-conductor phenomena such as effective lifetime, noise, and contact potentials can be made in a controlled manner. Modern wafer polishing methods such as the cupric ton or silicon dioxide technique and others can be evaluated in terms of effectiveness of damage removal. This invention is related to a United States Patent 4,018,626 entitled "Impact Sound Stressing for Semiconductor Devices by G.H. Sch?uttke and K.H. Yang, assigned to International Business Machines Corporation and issued April 19, 1977.

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