公开(公告)号：US3919060A

公开(公告)日：1975-11-11

申请号：US47932174

申请日：1974-06-14

Applicant: IBM

Inventor： POGGE H BERNHARD ,  POPONIAK MICHAEL R

IPC: H01L27/00 ,  C25F3/12 ,  H01L21/00 ,  H01L21/306 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  C25F3/00

CPC classification number: H01L21/76264 ,  C25F3/12 ,  H01L21/00 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/306 ,  H01L21/31662 ,  H01L21/7627 ,  H01L21/76281 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S438/911

Abstract: A semiconductor fabrication method for producing dielectrically isolated silicon regions wherein high conductivity regions surrounding device regions to be electrically isolated are produced in a silicon body, the high conductivity regions anodically etched in a solution to selectively produce regions of porous silicon, the body exposed to an oxidizing environment while heated to an elevated temperature to oxidize the resultant porous silicon regions.

Abstract translation: 一种半导体制造方法，用于制造介电隔离的硅区域，其中在硅体中产生围绕要被电隔离的器件区域的高导电性区域，在溶液中阳极蚀刻的高导电性区域以选择性地产生多孔硅的区域， 氧化环境，同时加热到升高的温度以氧化所得的多孔硅区域。

公开(公告)号：US3590372A

公开(公告)日：1971-06-29

申请号：US3590372D

申请日：1968-12-26

Applicant: IBM

Inventor： DESANTIS DOMINIC P ,  DESSAUER RALPH G ,  GOREY EDWARD F ,  POPONIAK MICHAEL R ,  SCHNEIDER CHRISTIAN P ,  SCHUMANN PAUL A JR

IPC: G01R27/00 ,  G01N27/04 ,  G01R1/067 ,  G01R31/28 ,  H01L21/66 ,  G01R27/14

CPC classification number: G01R31/2831 ,  G01N27/041 ,  G01R1/06705

Abstract: A three-point probe is employed to determine the spreading resistance of a material with the spreading resistance probe, which is common to both the current source and a voltage measuring means, being moved into engagement with the material after the other two probes are in engagement with the material. The velocity with which each of the probes engages the material is controlled and is variable. To ascertain that a good contact has been made by the spreading resistance probe and the magnitude of the current flowing through the material from the current source, the voltage measuring means is connected across resistance means in the wire from the current source to the spreading resistance probe and current is directed through the resistance means in opposite directions by flowing through the material between the spreading resistance probe and one of the other two probes. After the magnitude of the current has been determined, the voltage measuring means is connected to the spreading resistance probe adjacent its contact to the material and to the other of the two probes, which is not connected to the current source, to determine the voltage drop through the material due to current from the current source flowing in opposite directions through the material. The amount of difference between the two voltage readings on the specimen indicates if good contact is achieved.

公开(公告)号：US3493770A

公开(公告)日：1970-02-03

申请号：US3493770D

申请日：1966-03-01

Applicant: IBM

Inventor： DESSAUER RALPH G ,  PATZNER EUGENE J ,  POPONIAK MICHAEL R

IPC: C30B15/26 ,  H01L21/208 ,  H01J39/12 ,  G01N21/26

CPC classification number: C30B15/26 ,  Y10T117/1008 ,  Y10T117/1072

公开(公告)号：US3929529A

公开(公告)日：1975-12-30

申请号：US53091074

申请日：1974-12-09

Applicant: IBM

Inventor： POPONIAK MICHAEL R

IPC: H01L21/306 ,  H01L21/316 ,  H01L21/322 ,  H01L7/52

CPC classification number: H01L21/02016 ,  H01L21/0203 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/31662 ,  H01L21/3221 ,  Y10S148/015 ,  Y10S148/024 ,  Y10S148/037 ,  Y10S148/06 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/118 ,  Y10S148/122 ,  Y10S438/923 ,  Y10S438/96 ,  Y10S438/969

Abstract: A method for removing fast diffusing metal contaminants from a monocrystalline silicon body by (1) anodizing at least one side of the body in an aqueous liquid bath under conditions that result in the formation of a porous silicon surface layer, (2) annealing the resultant structure in a non-oxidizing environment, and (3) exposing the body to an oxidizing environment to oxidize the porous silicon layer to SiO2, or alternatively forming a capping layer over the porous silicon layer.

Abstract translation: 一种用于通过（1）在导致形成多孔硅表面层的条件下在水性液体浴中阳极氧化身体的至少一侧来消除单晶硅体中的快速扩散金属污染物的方法，（2）对所得物 结构在非氧化环境中，和（3）将体暴露于氧化环境以将多孔硅层氧化成SiO 2，或者在多孔硅层上形成覆盖层。

公开(公告)号：CA1039629A

公开(公告)日：1978-10-03

申请号：CA239201

申请日：1975-11-03

Applicant: IBM

Inventor： POPONIAK MICHAEL R

IPC: H01L21/306 ,  H01L21/316 ,  H01L21/322 ,  B01J17/34

Abstract: METHOD FOR GETTERING CONTAMINANTS IN MONOCRYSTALLINE SILICON A method for removing fast diffusing metal contaminants from a monocrystalline silicon body by (1) anodizing at least one side of the body in an aqueous liquid bath under conditions that result in the formation of a porous silicon surface layer, (2) annealing the resultant structure in a non-oxidizing environment, and (3) exposing the body to an oxidizing environment to oxidize the porous silicon layer to SiO2, or alternatively forming a capping layer over the porous silicon layer.

公开(公告)号：FR2344847A1

公开(公告)日：1977-10-14

申请号：FR7702072

申请日：1977-01-18

Applicant: IBM

Inventor： DEINES JOHN L ,  POPONIAK MICHAEL R ,  SCHWENKER ROBERT O

IPC: H01L21/66 ,  G01N27/00 ,  G01R31/26 ,  H01L21/306

公开(公告)号：CA1142266A

公开(公告)日：1983-03-01

申请号：CA360337

申请日：1980-09-16

Applicant: IBM

Inventor： HORNG CHENG T ,  POPONIAK MICHAEL R ,  RUPPRECHT HANS S ,  SCHWENKER ROBERT O

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/73 ,  H01L29/732 ,  H01L27/04

Abstract: A SELF-ALIGNED MICROMETER BIPOLAR TRANSISTOR DEVICE AND PROCESS A method for fabricating very high performance integrated circuit semiconductor devices. The method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. The fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultrahigh performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base. The P+ polysilicon layer which provides low base resistance is formed within the oxide isolation trenches, thus minimizing the parasitic capacitance. The transistor active base is formed in place by a low dosage boron implantation made with its concentration peak below the emitter. The device formed thus will have a controllable narrow base width and a FI9-79-021 low external base resistance. Both are essential to the high performance devices. The emitter of this invention structure is separated from the P+ polysilicon by a Si3N4/SiO2 composite dielectric layer. This dielectric separation ensures that electrons injected into the base do occur at the bottom of the emitter. The dielectric sleeve of the emitter also eliminates the sidewall hole current component normally existing in conventional transistors. Thus, the bipolar transistors formed by the disclosed process have a high emitter injection efficiency and also have high transistor current gains. Furthermore, the fabricated small geometry devices have planarized surface. The planarized device structure ensures the thin film covering which is critical to the integration of very small devices. FI 9-79-021

公开(公告)号：CA1090005A

公开(公告)日：1980-11-18

申请号：CA281576

申请日：1977-06-28

Applicant: IBM

Inventor： BEYER KLAUS D ,  DAS GOBINDA ,  POPONIAK MICHAEL R ,  YEH TSU-HSING

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/28 ,  H01L21/322 ,  H01L21/331 ,  H01L21/70

Abstract: SEMICONDUCTOR FABRICATION METHOD FOR IMPROVED DEVICE YIELD A method for fabricating bipolar semiconductor devices of large scale integration in which the formation of pipes, which result in shorts or leakages between two conductivity types of the semiconductor devices, is minimized. Prior to forming the emitters in the bipolar transistors, nucleation sites for crystallographic defects such as dislocation loops are formed in the base region near its surface. The emitters are then formed in base regions containing the nucleation sites and the sites are converted into electrically harmless dislocation loops during diffusion of the emitter impurity. Preferably, the nucleation sites are formed by implanting non-doping impurities, such as helium, neon, argon, krypton, xenon, silicon, and oxygen.

公开(公告)号：FR2294545A1

公开(公告)日：1976-07-09

申请号：FR7532211

申请日：1975-10-13

Applicant: IBM

Inventor： POPONIAK MICHAEL R

IPC: H01L21/306 ,  H01L21/316 ,  H01L21/322 ,  H01L21/46

公开(公告)号：CA1069221A

公开(公告)日：1980-01-01

申请号：CA272839

申请日：1977-02-28

Applicant: IBM

Inventor： DEINES JOHN L ,  POPONIAK MICHAEL R ,  SCHWENKER ROBERT O

IPC: H01L21/66 ,  G01N27/00 ,  G01R31/26 ,  H01L21/306

Abstract: ANODIC ETCHING METHOD FOR THE DETECTION OF ELECTRICALLY ACTIVE DEFECTS IN SILICON Electrically active defects, i.e., current-carrying defects or leakage paths in silicon crystals, are detected by an anodization process. The process selectively etches the crystal surface only where the electrically active defects are located when the anodization parameters are properly selected. Selected surface portions of the silicon structure are exposed to a hydrofluoric acid solution which is maintained at a negative potential with respect to the silicon structure. When the potential difference is set to a proper value, etch pits are formed in the surface of the silicon only at those locations overlying electrically active defects which impact device yield. The defects are observed and counted to provide a basis to predict yield of desired semiconductor devices to be formed later in the silicon structure.