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    7.
    发明专利
    未知

    公开(公告)号：DE3684380D1

    公开(公告)日：1992-04-23

    申请号：DE3684380

    申请日：1986-06-27

    Applicant: IBM

    Inventor： CSERVAK NANCY REBECCA ,  FRIBLEY SUSAN KAY ,  GOTH GEORGE RICHARD ,  TAKACS MARK ANTHONY

    IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/312 ,  H01L21/762

    Abstract: A semiconductor structure (30) having dielectric isolation trenches is provided with an overlaying organic polyimide layer (48) filling the deep trenches. After over-filling the trenches with the polyimide, the polyimide layer (48) is non-planar and has a thickness much larger in the low trench density regions (44) than that in the high density regions (46). A photoresist layer is then applied thereover, and controllably exposed using a mask which is the complement or inverse of the mask used for imaging the trench patterns to obtain a thick blockout photoresist mask (54,56,58,60) over the trenches and a thin wetting layer (52) of photoresist over the remainder of the substrate. Next, by means of a thermal step, the blockout photoresist is caused to reflow to form a relatively thick photoresist layer over the high trench density regions and a thin photoresist layer over the low trench density regions, thereby exactly compensating for the non-planarity of the polyimide layer.

    8.
    发明专利
    未知

    公开(公告)号：DE3483309D1

    公开(公告)日：1990-10-31

    申请号：DE3483309

    申请日：1984-11-23

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  HANSEN THOMAS ADRIAN ,  VILLETTO JR

    IPC: H01L29/78 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76 ,  H01L21/762 ,  H01L21/306

    Abstract: A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls (94) by precluding significant variation in etch bias during the trench formation.This is accomplished by interposing, between the conventionally formed imaging layer (86) of photoresist and the masking layer (84), two additional layers: one layer being an organic underlay (88) which is applied over the masking layer of SiO 2 (84); the other layer (90) applied over the oroanic laver and beina comoosed of silicon nitride or oxide.

    METHOD OF FORMING ADJACENT IMPURITY REGIONS OF DIFFERENT DOPING IN A SILICON SUBSTRATE
    9.
    发明专利
    METHOD OF FORMING ADJACENT IMPURITY REGIONS OF DIFFERENT DOPING IN A SILICON SUBSTRATE 未知

    公开(公告)号：DE2965185D1

    公开(公告)日：1983-05-19

    申请号：DE2965185

    申请日：1979-06-11

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/22 ,  H01L21/225 ,  H01L21/266 ,  H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L29/88 ,  H01L21/18 ,  H01L29/08

    Abstract: A method for forming adjacent impurity regions of differing conductivities in a semiconductor substrate without using lithography. N type impurities of a first conductivity are introduced into the substrate to form first impurity regions. The substrate is then oxidized to create a mask having a thickness which is greater over the N type impurity regions than over the remainder of the substrate. A portion of the masking layer is then removed, preferably by dip-etching, to a depth which is sufficient to re-expose the substrate only. Impurities of a second conductivity are then introduced in the substrate adjacent the N type impurity regions, with the remaining portion of the mask protecting the N type impurity regions from introduction of the second impurities therein.

    10.
    发明专利
    未知

    公开(公告)号：DE3687628T2

    公开(公告)日：1993-08-12

    申请号：DE3687628

    申请日：1986-10-28

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD

    IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06

    Abstract: In a semiconductor structure having two highly and similarly doped, e.g., P+ type, regions (26,30) embedded in close juxtaposition in a trench-isolated N type silicon mesa (22), N+ channel stops (40,42) embedded in the N type mesa between the P type regions, are provided. The channel stops are self-aligned to the walls of trench to arrest charge leakage between the P type regions due to parasitic transistor action along the trench wall. The P type regions may constitute two resistors, the emitter and collector of a lateral PNP transistor, etc. The dopant concentration in the channel stops is about one to two orders of magnitude higher than that in the N type silicon. A process of forming such channel stops introduces N type dopant into the exposed silicon followed by an anneal step to laterally diffuse the dopant into the silicon body. The exposed silicon is etched forming a deep trench which delineates silicon mesa having at a section of the peripheral portion thereof a shallow and highly N doped region.

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