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    2.
    发明专利
    未知

    公开(公告)号：DE3784117T2

    公开(公告)日：1993-08-12

    申请号：DE3784117

    申请日：1987-07-14

    Applicant: IBM

    Inventor： BONDUR JAMES ALLAN ,  GIAMMARCO NICHOLAS JAMES ,  HANSEN THOMAS ADRIAN ,  KAPLITA GEORGE ANTHONY ,  LECHATON JOHN S

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/263

    Abstract: Disclosed is a process for etching semiconductor materials with a high etch rate against an insulator mask using a novel etchant gas mixture. The mixture consists of a fluorochlorohydrocarbon (e.g., CCl2F2, CHCl2F2, CCl4 or CCl3F), SF6, O2 and an inert gas (e.g. He). The preferred gas mixture contains 2/1 ratio of the fluorochlorocarbon to SF6 and the following composition: 1-4 % of SF6, 3-10 % of O2, 74-93 % of He and 3-10 % of fluorochlorohydrocarbon. The etch rate of silicon (or silicide) against an oxide mask using this etchant gas mixture under normal etching conditions is high, on the order of 30-40. An impressive feature of the process is shape control of trenches by mere manipulation of the RIE system power.

    3.
    发明专利
    未知

    公开(公告)号：DE3586554T2

    公开(公告)日：1993-04-08

    申请号：DE3586554

    申请日：1985-06-03

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  HANSEN THOMAS ADRIAN ,  MAKRIS JAMES STEVE

    IPC: H01L21/761 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L29/41

    Abstract: Deep trenches (14, 15) are formed according to the desired pattern through the N epitaxial layer (13) and N + subcollector region (12) into the P- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon material. Channel stop regions (18) are formed e.g. by ion implantation of boron atoms at the bottom of trenches. Si0 2 and Si 3 N 4 layers (17, 19) are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose one side of the trench sidewalls, the bottom of the trenches adjacent thereto and others areas if desired such as the top surface of the stud. The composite SiO 2 /Si 3 N 4 layer is then etched to leave exposed only the sidewalls of the stud, at least partially the bottom of the trenches adjacent thereto and the top surface of the stud. Platinum is deposited preferably via sputter deposition, conformally coating all regions of the structure. After sintering, the unreacted platinum is removed using wet chemical etch (aqua regia). Platinum silicide is left in all opened contacts and on the stud sidewalls where its defines a metal silicide lining (25) or cap, covering the stud. This lining connects the top surface (25a) of the stud, with the channel stop implanted regions (18) and thence forms the desired substrate contact.

    5.
    发明专利
    未知

    公开(公告)号：DE3784117D1

    公开(公告)日：1993-03-25

    申请号：DE3784117

    申请日：1987-07-14

    Applicant: IBM

    Inventor： BONDUR JAMES ALLAN ,  GIAMMARCO NICHOLAS JAMES ,  HANSEN THOMAS ADRIAN ,  KAPLITA GEORGE ANTHONY ,  LECHATON JOHN S

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/263

    Abstract: Disclosed is a process for etching semiconductor materials with a high etch rate against an insulator mask using a novel etchant gas mixture. The mixture consists of a fluorochlorohydrocarbon (e.g., CCl2F2, CHCl2F2, CCl4 or CCl3F), SF6, O2 and an inert gas (e.g. He). The preferred gas mixture contains 2/1 ratio of the fluorochlorocarbon to SF6 and the following composition: 1-4 % of SF6, 3-10 % of O2, 74-93 % of He and 3-10 % of fluorochlorohydrocarbon. The etch rate of silicon (or silicide) against an oxide mask using this etchant gas mixture under normal etching conditions is high, on the order of 30-40. An impressive feature of the process is shape control of trenches by mere manipulation of the RIE system power.

    6.
    发明专利
    未知

    公开(公告)号：DE3483309D1

    公开(公告)日：1990-10-31

    申请号：DE3483309

    申请日：1984-11-23

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  HANSEN THOMAS ADRIAN ,  VILLETTO JR

    IPC: H01L29/78 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76 ,  H01L21/762 ,  H01L21/306

    Abstract: A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls (94) by precluding significant variation in etch bias during the trench formation.This is accomplished by interposing, between the conventionally formed imaging layer (86) of photoresist and the masking layer (84), two additional layers: one layer being an organic underlay (88) which is applied over the masking layer of SiO 2 (84); the other layer (90) applied over the oroanic laver and beina comoosed of silicon nitride or oxide.

    8.
    发明专利
    未知

    公开(公告)号：DE3586554D1

    公开(公告)日：1992-10-01

    申请号：DE3586554

    申请日：1985-06-03

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  HANSEN THOMAS ADRIAN ,  MAKRIS JAMES STEVE

    IPC: H01L21/761 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L29/41

    Abstract: Deep trenches (14, 15) are formed according to the desired pattern through the N epitaxial layer (13) and N + subcollector region (12) into the P- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon material. Channel stop regions (18) are formed e.g. by ion implantation of boron atoms at the bottom of trenches. Si0 2 and Si 3 N 4 layers (17, 19) are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose one side of the trench sidewalls, the bottom of the trenches adjacent thereto and others areas if desired such as the top surface of the stud. The composite SiO 2 /Si 3 N 4 layer is then etched to leave exposed only the sidewalls of the stud, at least partially the bottom of the trenches adjacent thereto and the top surface of the stud. Platinum is deposited preferably via sputter deposition, conformally coating all regions of the structure. After sintering, the unreacted platinum is removed using wet chemical etch (aqua regia). Platinum silicide is left in all opened contacts and on the stud sidewalls where its defines a metal silicide lining (25) or cap, covering the stud. This lining connects the top surface (25a) of the stud, with the channel stop implanted regions (18) and thence forms the desired substrate contact.

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