公开(公告)号：DE3483309D1

公开(公告)日：1990-10-31

申请号：DE3483309

申请日：1984-11-23

Applicant: IBM

Inventor： GOTH GEORGE RICHARD ,  HANSEN THOMAS ADRIAN ,  VILLETTO JR

IPC: H01L29/78 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76 ,  H01L21/762 ,  H01L21/306

Abstract: A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls (94) by precluding significant variation in etch bias during the trench formation.This is accomplished by interposing, between the conventionally formed imaging layer (86) of photoresist and the masking layer (84), two additional layers: one layer being an organic underlay (88) which is applied over the masking layer of SiO 2 (84); the other layer (90) applied over the oroanic laver and beina comoosed of silicon nitride or oxide.