公开(公告)号：WO0208904A3

公开(公告)日：2002-05-02

申请号：PCT/GB0102984

申请日：2001-07-05

Applicant: IBM ,  IBM UK

Inventor： ADAMS ROBERT DEAN ,  ECKENRODE THOMAS ,  GREGOR STEVEN ,  ZARRINEH KAMRAN

IPC: G01R31/28 ,  G06F12/16 ,  G11C29/12 ,  G11C29/16 ,  G11C29/00

CPC classification number: G11C29/16 ,  G11C2029/0401

Abstract: The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.

Abstract translation: 用于测试集成电路的嵌入式存储器结构的可编程存储器内置自检（BIST）布置的功能被扩展到系统级测试，以在集成电路和包括它们的板被放置在其中之后确定系统的可操作性 通过生成在外部测试仪不提供测试指令时加载到指令存储模块中的默认测试信号，可以在更大的系统中进行服务。 BIST安排的这一附加功能可以提高芯片空间利用率，提高系统级测试。 在芯片制造和/或电路板组装期间从外部测试仪装载测试指令不受影响。

公开(公告)号：AT260484T

公开(公告)日：2004-03-15

申请号：AT01943709

申请日：2001-07-05

Applicant: IBM

Inventor： ADAMS ROBERT DEAN ,  ECKENRODE THOMAS ,  GREGOR STEVEN ,  ZARRINEH KAMRAN

IPC: G01R31/28 ,  G06F12/16 ,  G11C29/12 ,  G11C29/16 ,  G06F12/00

Abstract: The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.

公开(公告)号：DE60102164D1

公开(公告)日：2004-04-01

申请号：DE60102164

申请日：2001-07-05

Applicant: IBM

Inventor： ADAMS DEAN ,  ECKENRODE THOMAS ,  GREGOR STEVEN ,  ZARRINEH KAMRAN

IPC: G01R31/28 ,  G06F12/16 ,  G11C29/12 ,  G11C29/16 ,  G06F12/00

Abstract: The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.

公开(公告)号：DE60102164T2

公开(公告)日：2004-09-30

申请号：DE60102164

申请日：2001-07-05

Applicant: IBM

Inventor： ADAMS DEAN ,  ECKENRODE THOMAS ,  GREGOR STEVEN ,  ZARRINEH KAMRAN

IPC: G01R31/28 ,  G06F12/16 ,  G11C29/12 ,  G11C29/16 ,  G06F12/00

Abstract: The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.

公开(公告)号：AU6624001A

公开(公告)日：2002-02-05

申请号：AU6624001

申请日：2001-07-05

Applicant: IBM

Inventor： ECKENRODE THOMAS ,  GREGOR STEVEN ,  ZARRINEH KAMRAN

IPC: G01R31/28 ,  G06F12/16 ,  G11C29/12 ,  G11C29/16 ,  G06F12/00

Abstract: The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.