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公开(公告)号:HK1180804A1
公开(公告)日:2013-10-25
申请号:HK13108102
申请日:2013-07-10
Applicant: IBM
Inventor: GREINER DAN D , OSISEK DAMIAN LEO DL , SLEGEL TIMOTHY T , HELLER LISA L
IPC: G06F20060101
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公开(公告)号:HK1207441A1
公开(公告)日:2016-01-29
申请号:HK15108072
申请日:2015-08-20
Applicant: IBM
Inventor: GREINER DAN D , SITTMANN GUSTAV G
IPC: G06F20060101
Abstract: A computer implemented instruction is executed. One or more translation table entry locations (TLB) are specified by the instruction. Based on a local-clearing (LC) control specified by the instruction being a first value, the processor selectively clears TLBs in a plurality of the CPUs in a configuration of entries corresponding to the determined translation table entry location. Based on the local-clearing (LC) being a second value, the processor selectively clears only the TLBs of the CPU executing the instruction of entries corresponding to the determined translation table entry location. A computer program product, computer system and computer implemented method are provided.
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公开(公告)号:HK1210846A1
公开(公告)日:2016-05-06
申请号:HK15111617
申请日:2015-11-25
Applicant: IBM
Inventor: GREINER DAN D , ROGERS ROBERT R , SITTMANN GUSTAV G
IPC: G06F20060101
Abstract: A first and a second operand are compared. If they are equal, the contents of register R1+1 are stored at the second-operand location, and the specified CPU or CPUs in the configuration are cleared of all TLB table entries of the designated type formed through the use of the replaced entry in storage, and all lower-level TLB table entries formed through the use of the cleared higher-level TLB table entries. A valid DAT table entry is replaced with a new entry, and the Translation Lookaside Buffer (TLB) is purged of any copies of (at least) the single entry on all CPUs in the configuration. If the first and second operands are unequal, the second operand is loaded at the first-operand location. The comparison result is indicated by the condition code. A method, system and a computer program product are provided.
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公开(公告)号:HK1207442A1
公开(公告)日:2016-01-29
申请号:HK15108073
申请日:2015-08-20
Applicant: IBM
Inventor: GREINER DAN D , JACOBI CHRISTIAN C , SLEGEL TIMOTHY T , MITRAN MARCEL M
IPC: G06F20060101
Abstract: Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.
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公开(公告)号:HK1180802A1
公开(公告)日:2013-10-25
申请号:HK13108100
申请日:2013-07-10
Applicant: IBM
Inventor: GREINER DAN D , CRADDOCK DAVID D , GREGG THOMAS T , FARRELL MARK M
IPC: G06F20060101
Abstract: Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter.
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公开(公告)号:HK1180794A1
公开(公告)日:2013-10-25
申请号:HK13108051
申请日:2013-07-09
Applicant: IBM
Inventor: CRADDOCK DAVID D , GREINER DAN D , SCHMIDT DONALD WILLIAM DW , GREGG THOMAS T
IPC: G06F20060101
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公开(公告)号:HK1180803A1
公开(公告)日:2013-10-25
申请号:HK13108101
申请日:2013-07-10
Applicant: IBM
Inventor: CRADDOCK DAVID D , FARRELL MARK M , GREGG THOMAS T , GLENDENING BETH B , GREINER DAN D
IPC: G06F20060101
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公开(公告)号:HK1180799A1
公开(公告)日:2013-10-25
申请号:HK13108097
申请日:2013-07-10
Applicant: IBM
Inventor: GREINER DAN D , CRADDOCK DAVID D , GREGG THOMAS T , FARRELL MARK M
IPC: G06F20060101
Abstract: Communication with adapters of a computing environment is facilitated. Control instructions specifically designed for communicating data to and from adapters are provided to facilitate the communication. The instructions explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter, such as a Peripheral Component Interconnect (PCI) or Peripheral Component Interconnect Express (PCIe) adapter.
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公开(公告)号:HK1180793A1
公开(公告)日:2013-10-25
申请号:HK13108049
申请日:2013-07-09
Applicant: IBM
Inventor: CRADDOCK DAVID D , GREGG THOMAS T , GREINER DAN D , LAIS ERIC NORMAN EN
IPC: G06F20060101
Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.
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