公开(公告)号：DE3175419D1

公开(公告)日：1986-11-06

申请号：DE3175419

申请日：1981-10-20

Applicant: IBM

Inventor： GRISE GARY DOUGLAS ,  HSIEH NING ,  KALTER HOWARD LEO ,  LAM CHUNG HON

IPC: G11C14/00 ,  G11C11/34 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

Abstract: A memory system, particularly an electrically alterable read only memory system which includes a semiconductor substrate (10) having a diffusion region (12) therein defining one end of a channel region (14), a control plate (22, T1), a floating plate (20) separated from the channel region by a thin dielectric layer (16) and disposed between the control plate (22) and the channel region (14) and means (T1-T3) for transferring charge to and from the floating plate (22). A control gate (32) is coupled to the channel region (14) and is located between the diffusion region (12) and the floating plate (22). The control gate (32) may be connected to a word line and the diffusion region (12) may be connected to a bit/sense line. The channel region (14) is controlled by the word line and the presence or absence of charge on the floating plate (20). Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate (20). The charge transfer means (T1, T3) includes an enhanced conduction insulator (24) and means (T1-T3) for applying appropriate voltages to the control plate (22) and to the control gate (32) to transfer charge to and from the floating plate (20) through the enhanced conduction insulator (24).

公开(公告)号：DE3279165D1

公开(公告)日：1988-12-01

申请号：DE3279165

申请日：1982-12-02

Applicant: IBM

Inventor： GAFFNEY DONALD PAUL ,  GRISE GARY DOUGLAS ,  LAM CHUNG HON

IPC: G11C14/00 ,  G11C17/00 ,  G11C17/04 ,  H01L27/105 ,  G11C11/00

Abstract: This invention provides improved non-volatile semiconductor memories which form non-inverting signals and which include a one device dynamic volatile memory circuit having a storage capacitor (C,) which includes a conductive plate (12), a charged floating gate (FG) and an inversion layer (10) in a semiconductor substrate (18) together with a non-volatile device including the floating gate (FG), a control electrode (24) and a voltage divider having first and second serially-connected capacitors (C2, C1), with the floating gate (FG) being disposed at the common point between the first and second capacitors (C2, C1). The plate (12) of the storage capacitor (C,) is connected to a reference voltage source. The control electrode (24) is capacitively coupled to the floating gate (FG) through the first capacitor (C2) which includes a charge or electron injector structure. The capacitance of the first capacitor (C2) has a value, preferably, substantially less than that of the second capacitor (C1) which is formed between the floating gate (FG) and the semiconductor substrate (18).