公开(公告)号：IT1162577B

公开(公告)日：1987-04-01

申请号：IT2532879

申请日：1979-08-29

Applicant: IBM

Inventor： CLEMEN RAINER ,  GSCHWENDTNER JOERG ,  HAUG WERNER

IPC: G11C11/41 ,  G11C11/24 ,  G11C11/408 ,  G11C11/413 ,  H03K3/353 ,  H03K3/356 ,  H03K5/02 ,  H03K5/15 ,  H03K19/0185 ,  H03K

Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

公开(公告)号：IT1162599B

公开(公告)日：1987-04-01

申请号：IT2781279

申请日：1979-12-04

Applicant: IBM

Inventor： CLEMEN RAINER ,  GSCHWENDTNER JOERG ,  HAUG WERNER

IPC: G11C11/409 ,  G11C7/00 ,  G11C11/24 ,  G11C11/403 ,  G11C11/404 ,  G11C11/4096 ,  G11B

公开(公告)号：FR2385179A1

公开(公告)日：1978-10-20

申请号：FR7804979

申请日：1978-02-15

Applicant: IBM

Inventor： ARZUBI LUIS ,  GSCHWENDTNER JOERG ,  SCHNADT ROBERT

IPC: G11C11/409 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/00 ,  G11C11/34

Abstract: A high performance semiconductor memory read/write data access circuit including a sense amplifier directly coupled to a pair of bit lines is provided with a pair of bit switching devices to enable data communication external to the memory. Control potentials and timing of switching signals are provided in such a manner that only one of the bit switches becomes conductive during reading and writing access to the memory.