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    Logically controlled inverter
    1.
    发明授权
    Logically controlled inverter 失效
    逻辑控制变频器

    公开(公告)号：US3875426A

    公开(公告)日：1975-04-01

    申请号：US26301772

    申请日：1972-06-15

    Applicant: IBM

    Inventor： BAITINGER OTZ ,  HAUG WERNER

    IPC: H03K5/02 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/096 ,  H03K19/08 ,  H03K19/34 ,  H03K19/36 ,  H03K19/40

    CPC classification number: H03K19/01742 ,  H03K5/023 ,  H03K19/01714 ,  H03K19/01721 ,  H03K19/01735 ,  H03K19/09441 ,  H03K19/096

    Abstract: Disclosed is an inverter circuit consisting of a first fieldeffect transistor connected in series to a capacitive load and a second field-effect transistor connected in parallel to said load, whereby charging and discharging of the capacitive load are effected via the first and second field-effect transistor, respectively, and a defined potential is applied to the capacitive load via a third field-effect transistor when the first field-effect transistor is inhibited.

    Abstract translation: 公开了一种逆变器电路，其由与电容性负载串联连接的第一场效应晶体管和与所述负载并联连接的第二场效应晶体管组成，由此容性负载的充电和放电经由第一和第二场 并且当禁止第一场效应晶体管时，经由第三场效应晶体管将限定的电位施加到电容性负载。

    INPUT CIRCUIT FOR AN INTEGRATED MONOLITHIC SEMICONDUCTOR MEMORY USING FIELD EFFECT TRANSISTORS
    2.
    发明专利
    INPUT CIRCUIT FOR AN INTEGRATED MONOLITHIC SEMICONDUCTOR MEMORY USING FIELD EFFECT TRANSISTORS 未知

    公开(公告)号：DE3169127D1

    公开(公告)日：1985-04-04

    申请号：DE3169127

    申请日：1981-05-13

    Applicant: IBM DEUTSCHLAND ,  IBM

    Inventor： HAUG WERNER ,  CLEMEN RAINER

    IPC: G11C8/06 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/417 ,  H03K19/017 ,  H03K19/094 ,  G11C8/00 ,  G11C11/24 ,  G11C11/40

    Abstract: An input circuit for a field effect transistor (FET) storage is described which consists of a bootstrap inverter which by a dynamically operating charge-up circuit is supplemented for charging up the bootstrap node to the full operating voltage, and which can be directly controlled with TTL levels without a level converter consisting of bipolar transistors being inserted. For that purpose, the input electrode of the bootstrap capacitor of the dynamically operating charge-up circuit is connected to the output of an inverter following the input circuit. Furthermore a discharge branch is provided for the node of the dynamically operating charge-up circuit. With its other end, together with the gate of the charge-up field effect transistor of the dynamic charge-up circuit, the discharge branch is connected to the output of another inverter following the first one. It is thus assured that when owing to the bootstrap effect the potential of the bootstrap node rises over the value VH of the operating voltage, this node cannot be discharged via the FET's in the charge-up circuit to the positive pole of the operating voltage source. This would counteract the rise of the potential of the bootstrap node so that the potential and the output of the input circuit would rise only slowly, and would not reach the full value VH of the operating voltage.

    8.
    发明专利
    未知

    公开(公告)号：IT7925328D0

    公开(公告)日：1979-08-29

    申请号：IT2532879

    申请日：1979-08-29

    Applicant: IBM

    Inventor： CLEMEN RAINER ,  JOERG GSCHWENDTNER ,  HAUG WERNER

    IPC: G11C11/41 ,  G11C11/24 ,  G11C11/408 ,  G11C11/413 ,  H03K3/353 ,  H03K3/356 ,  H03K5/02 ,  H03K5/15 ,  H03K19/0185 ,  H03K

    Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

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