中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.018 seconds)

    High-speed single end sensing by constructible half latch
    1.
    发明专利
    High-speed single end sensing by constructible half latch 有权
    高速单端感测由构造半长型

    公开(公告)号：JP2000076869A

    公开(公告)日：2000-03-14

    申请号：JP19606299

    申请日：1999-07-09

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

    Inventor： CLEMEN RAINER ,  MIELICH HERALD ,  PILLE JUERGEN

    IPC: G11C7/06 ,  G11C11/419 ,  G11C29/12 ,  G11C29/00

    CPC classification number: G11C7/065 ,  G11C7/067 ,  G11C11/419

    Abstract: PROBLEM TO BE SOLVED: To match and adjust a drift on a bit line to a high-speed system execution mode or low-power test mode in accordance with a feed voltage by using a small skew invertor with a switchable PFET feedback loop.
    SOLUTION: Gate terminals of PFETs P1, P21 are connected to an output of an invertor I1 which is in turn connected to a bit line BL. A signal 'test' is low in a system execution mode. When '1' is to be read from a memory cell, the PFET P1 is turned on and works as a bleeder element to prevent the bit line BL from drifting towards a feed voltage Vdd because of a threshold or smaller current. The signal 'test' is high in a test mode, wherein the PFET P1 works as a keeper element and constitutes a half latch with the invertor I1. The keeper element PFET P1 is reinforced in function by a parallel keeper route of PFETs P21, P22.
    COPYRIGHT: (C)2000,JPO

    Abstract translation: 要解决的问题：通过使用具有可切换PFET反馈回路的小偏斜逆变器，根据馈电电压将位线上的漂移与高速系统执行模式或低功耗测试模式相匹配和调整。 解决方案：PFET P1，P21的栅极端子连接到逆变器I1的输出，反相器I1又连接到位线BL。 信号“测试”在系统执行模式中为低。 当从存储单元读取'1'时，PFET P1导通，并作为泄放元件工作，以防止位线BL由于阈值或更小的电流而向馈送电压Vdd漂移。 信号“测试”在测试模式下很高，其中PFET P1用作保持器元件并且构成具有反相器I1的半锁存器。 保持元件PFET P1通过PFET P21，P22的平行保持器路径功能被加强。

    INPUT CIRCUIT FOR AN INTEGRATED MONOLITHIC SEMICONDUCTOR MEMORY USING FIELD EFFECT TRANSISTORS
    2.
    发明专利
    INPUT CIRCUIT FOR AN INTEGRATED MONOLITHIC SEMICONDUCTOR MEMORY USING FIELD EFFECT TRANSISTORS 未知

    公开(公告)号：DE3169127D1

    公开(公告)日：1985-04-04

    申请号：DE3169127

    申请日：1981-05-13

    Applicant: IBM DEUTSCHLAND ,  IBM

    Inventor： HAUG WERNER ,  CLEMEN RAINER

    IPC: G11C8/06 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/417 ,  H03K19/017 ,  H03K19/094 ,  G11C8/00 ,  G11C11/24 ,  G11C11/40

    Abstract: An input circuit for a field effect transistor (FET) storage is described which consists of a bootstrap inverter which by a dynamically operating charge-up circuit is supplemented for charging up the bootstrap node to the full operating voltage, and which can be directly controlled with TTL levels without a level converter consisting of bipolar transistors being inserted. For that purpose, the input electrode of the bootstrap capacitor of the dynamically operating charge-up circuit is connected to the output of an inverter following the input circuit. Furthermore a discharge branch is provided for the node of the dynamically operating charge-up circuit. With its other end, together with the gate of the charge-up field effect transistor of the dynamic charge-up circuit, the discharge branch is connected to the output of another inverter following the first one. It is thus assured that when owing to the bootstrap effect the potential of the bootstrap node rises over the value VH of the operating voltage, this node cannot be discharged via the FET's in the charge-up circuit to the positive pole of the operating voltage source. This would counteract the rise of the potential of the bootstrap node so that the potential and the output of the input circuit would rise only slowly, and would not reach the full value VH of the operating voltage.

    3.
    发明专利
    未知

    公开(公告)号：IT1162577B

    公开(公告)日：1987-04-01

    申请号：IT2532879

    申请日：1979-08-29

    Applicant: IBM

    Inventor： CLEMEN RAINER ,  GSCHWENDTNER JOERG ,  HAUG WERNER

    IPC: G11C11/41 ,  G11C11/24 ,  G11C11/408 ,  G11C11/413 ,  H03K3/353 ,  H03K3/356 ,  H03K5/02 ,  H03K5/15 ,  H03K19/0185 ,  H03K

    Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

    9.
    发明专利
    未知

    公开(公告)号：IT7925328D0

    公开(公告)日：1979-08-29

    申请号：IT2532879

    申请日：1979-08-29

    Applicant: IBM

    Inventor： CLEMEN RAINER ,  JOERG GSCHWENDTNER ,  HAUG WERNER

    IPC: G11C11/41 ,  G11C11/24 ,  G11C11/408 ,  G11C11/413 ,  H03K3/353 ,  H03K3/356 ,  H03K5/02 ,  H03K5/15 ,  H03K19/0185 ,  H03K

    Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

    10.
    发明专利
    未知

    公开(公告)号：DE69920830T2

    公开(公告)日：2005-10-13

    申请号：DE69920830

    申请日：1999-06-19

    Applicant: IBM

    Inventor： CLEMEN RAINER ,  MIELICH HARALD ,  PILLE JUERGEN

    IPC: G11C7/06 ,  G11C11/419 ,  G11C29/12 ,  G11C7/00 ,  G11C29/00

    Abstract: For high-speed single-ended sensing of the signal from a (multi-port) SRAM cell, a configurable half-latch with 2 PFET feedback pathes is proposed, which can be set up either as a bleeder device in the system mode or as keeper devices in the test modes, controlled by a DC signal (TEST). The bleeder and keepers are attached to the bit line and gated by a small ratioed inverter serving as sense amplifier. In case of system mode, a low control signal is applied to the source of the bleeder to limit the bit line up-level to a threshold below the supply voltage Vdd. Thus, discharging the bit line when reading a '0' is fast. Reading a '1' is also fast by skewing the inverter to a PFET/NFET ratio below 1. For chip testing, the control signal is set high to enable the keepers which restore the bit line close to the supply voltage, even when large subthreshold currents try to discharge it via the unselected cells. This turns off the PFET of the inverter, thereby minimizing the DC current. The new approach improves the access time by about 10%, since no speed must be sacrificed for low-power operation during reliability tests at high voltage (1.5x to 2x Vdd) and temperature.

Patent Agency Ranking