公开(公告)号：FR2279153A1

公开(公告)日：1976-02-13

申请号：FR7517191

申请日：1975-05-27

Applicant: IBM

Inventor： BODNER RONALD E ,  CROOKS THOMAS L ,  GUEST JOHN E ,  MAGRISSO ISRAEL B ,  SLACK KEITH K

IPC: G06F13/12 ,  G06F13/18 ,  G06F13/28 ,  G06F3/00

Abstract: Control circuitry in a computer system is responsive to an allow cycle steal signal from an I/O attachment operating in a burst or dedicated data transfer mode and generates control signals whereby the next data storage cycle is made available to an I/O device which is also capable of operating in a cycle steal mode. Upon completion of the next storage cycle, the operation reverts to burst mode and the I/O attachment operating in the burst mode is granted ensuing data storage cycles until it relinquishes a storage cycle to an I/O device capable of using and having a need for it.