公开(公告)号：FR2296883A1

公开(公告)日：1976-07-30

申请号：FR7534731

申请日：1975-11-07

Applicant: IBM

Inventor： BODNER RONALD E ,  CROOKS THOMAS L ,  MAGRISSO ISRAEL B ,  CIANCIOSI MARIO N ,  SLACK KEITH K ,  SMITH RICHARD S

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/42

Abstract: Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock. The CPU clock runs and the storage clock can be activated depending upon the type of I/O instruction being executed, the CPU clock runs until it reaches a second particular time state and then remains at that particular time state until the port again generates an advance time signal to the CPU. The activity taking place as the CPU clock is advancing depends upon the type of I/O instruction, but generally a data transfer occurs, and the data is entered into or transferred from local storage registers or main or control storage. The extended second particular time state is used for a de-synchronization sequence between the port and I/O attachment.

公开(公告)号：CA1137644A

公开(公告)日：1982-12-14

申请号：CA347544

申请日：1980-03-12

Applicant: IBM

Inventor： HAMMER WILLIAM E ,  LEWIS DAVID O ,  REED JOHN W ,  ROBINSON THOMAS S ,  SLACK KEITH K

IPC: G06F13/00

Abstract: ALLOCATING AND RESOLVING NEXT VIRTUAL PAGES FOR INPUT/OUTPUT In a paged, virtual memory computer system an apparatus is provided for enabling I/O device adapters to request the CPU to allocate or resolve virtual pages into main storage pages as required for I/O data transfers. The I/O adapter provides the channel virtual address information specifying the requested page and channel function information which indicates whether the requested page is to be transferred from secondary storage into main storage or merely allocated as a page in main storage. The channel forms the virtual address information and the channel function information into a page request function event which is stored in an I/O event stack in main storage for retrieval and processing by the CPU. RO9-78-035

公开(公告)号：DE2965202D1

公开(公告)日：1983-05-19

申请号：DE2965202

申请日：1979-09-24

Applicant: IBM

Inventor： MCCULLOUGH WARREN J ,  POLAND TERRELL A ,  REYNOLDS DALE N ,  SLACK KEITH K ,  TURNER RICHARD T

IPC: G06F9/46 ,  G06F9/40

公开(公告)号：CA1050664A

公开(公告)日：1979-03-13

申请号：CA239420

申请日：1975-11-12

Applicant: IBM

Inventor： BODNER RONALD E ,  CIANCIOSI MARIO N ,  CROOKS THOMAS L ,  MAGRISSO ISRAEL B ,  SLACK KEITH K ,  SMITH RICHARD S

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/42

Abstract: DATA TRANSFER CONTROL SYSTEM Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If a I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock. The CPU clock runs and the storage clock can be activated depending upon the type of I/O instruction being executed, the CPU clock runs until it reaches a second particular time state and then remains at that particular time state until the port again generates an advance time signal to the CPU. The activity taking place as the CPU clock is advancing depends upon the type of I/O instruction, but generally a data transfer occurs, and the data is entered into or transferred from local storage registers or main or control storage. The extended second particular time state is used for a de-synchroniza-tion sequence between the port and I/O attachment.

公开(公告)号：FR2279153A1

公开(公告)日：1976-02-13

申请号：FR7517191

申请日：1975-05-27

Applicant: IBM

Inventor： BODNER RONALD E ,  CROOKS THOMAS L ,  GUEST JOHN E ,  MAGRISSO ISRAEL B ,  SLACK KEITH K

IPC: G06F13/12 ,  G06F13/18 ,  G06F13/28 ,  G06F3/00

Abstract: Control circuitry in a computer system is responsive to an allow cycle steal signal from an I/O attachment operating in a burst or dedicated data transfer mode and generates control signals whereby the next data storage cycle is made available to an I/O device which is also capable of operating in a cycle steal mode. Upon completion of the next storage cycle, the operation reverts to burst mode and the I/O attachment operating in the burst mode is granted ensuing data storage cycles until it relinquishes a storage cycle to an I/O device capable of using and having a need for it.