公开(公告)号：FR2296883A1

公开(公告)日：1976-07-30

申请号：FR7534731

申请日：1975-11-07

Applicant: IBM

Inventor： BODNER RONALD E ,  CROOKS THOMAS L ,  MAGRISSO ISRAEL B ,  CIANCIOSI MARIO N ,  SLACK KEITH K ,  SMITH RICHARD S

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/42

Abstract: Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock. The CPU clock runs and the storage clock can be activated depending upon the type of I/O instruction being executed, the CPU clock runs until it reaches a second particular time state and then remains at that particular time state until the port again generates an advance time signal to the CPU. The activity taking place as the CPU clock is advancing depends upon the type of I/O instruction, but generally a data transfer occurs, and the data is entered into or transferred from local storage registers or main or control storage. The extended second particular time state is used for a de-synchronization sequence between the port and I/O attachment.

公开(公告)号：FR2293744A1

公开(公告)日：1976-07-02

申请号：FR7532209

申请日：1975-10-13

Applicant: IBM

Inventor： BODNER RONALD E ,  CROOKS THOMAS L ,  MAGRISSO ISRAEL B ,  SLAC KEITH K

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/06

公开(公告)号：CA1199416A

公开(公告)日：1986-01-14

申请号：CA440692

申请日：1983-11-08

Applicant: IBM

Inventor： KELLEY RICHARD A ,  KURTZ HOBART L ,  MAGRISSO ISRAEL B ,  QUANSTROM JACK L

IPC: G06F13/37 ,  G06F13/14 ,  G06F13/20

Abstract: An arbitration technique is described for use in conjunction with a parallel bus structure. Essentially, it involves the use of a Request signal instead of an Acknowledge signal as the propagated polling signal and making use of the delay elements in each bus unit, which act in parallel with poll propagation and with each other to reduce the net poll propagation time. Making use of the Request signal allows initiation of arbitration prior to the activation time of the Acknowledge line.

公开(公告)号：BR8306942A

公开(公告)日：1984-07-24

申请号：BR8306942

申请日：1983-12-18

Applicant: IBM

Inventor： KELLEY RICHARD A ,  KURTZ HOBART L ,  MAGRISSO ISRAEL B ,  QUANSTROM JACK L

IPC: G06F13/37 ,  G06F15/16 ,  G06F9/46

公开(公告)号：CA1050664A

公开(公告)日：1979-03-13

申请号：CA239420

申请日：1975-11-12

Applicant: IBM

Inventor： BODNER RONALD E ,  CIANCIOSI MARIO N ,  CROOKS THOMAS L ,  MAGRISSO ISRAEL B ,  SLACK KEITH K ,  SMITH RICHARD S

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/42

Abstract: DATA TRANSFER CONTROL SYSTEM Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If a I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock. The CPU clock runs and the storage clock can be activated depending upon the type of I/O instruction being executed, the CPU clock runs until it reaches a second particular time state and then remains at that particular time state until the port again generates an advance time signal to the CPU. The activity taking place as the CPU clock is advancing depends upon the type of I/O instruction, but generally a data transfer occurs, and the data is entered into or transferred from local storage registers or main or control storage. The extended second particular time state is used for a de-synchroniza-tion sequence between the port and I/O attachment.

公开(公告)号：FR2279153A1

公开(公告)日：1976-02-13

申请号：FR7517191

申请日：1975-05-27

Applicant: IBM

Inventor： BODNER RONALD E ,  CROOKS THOMAS L ,  GUEST JOHN E ,  MAGRISSO ISRAEL B ,  SLACK KEITH K

IPC: G06F13/12 ,  G06F13/18 ,  G06F13/28 ,  G06F3/00

Abstract: Control circuitry in a computer system is responsive to an allow cycle steal signal from an I/O attachment operating in a burst or dedicated data transfer mode and generates control signals whereby the next data storage cycle is made available to an I/O device which is also capable of operating in a cycle steal mode. Upon completion of the next storage cycle, the operation reverts to burst mode and the I/O attachment operating in the burst mode is granted ensuing data storage cycles until it relinquishes a storage cycle to an I/O device capable of using and having a need for it.