公开(公告)号：JP2004207714A

公开(公告)日：2004-07-22

申请号：JP2003413993

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  GUY M COEN ,  IEONG MEIKEI ,  ROY RONNEN A ,  SOLOMON PAUL M ,  YANG MIN

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate field effect transistor (DGFET) structure which can noticeably reduce the parasitic capacitance under its source/drain region, and its manufacturing method.
SOLUTION: This double-gate field effect transistor (DGFET) adopts new two means for reducing the parasitic capacitance under its source/drain region. One means is as follows: a silicon region outside a gate is converted into an oxide 44, while a silicon/ledge 46 adjacent to the gate 58 is protected with a first spacer having a first width. This oxidation can be performed easily by means of implantation of self-aligned oxygen ions or other ions. The other means is to have the first spacer removed and replaced with a second spacer 48 which has a width smaller than that of the first one, and a new silicon source/drain region 60 formed under a self-aligned isolation region 56 by lateral selective full overgrowth, by using the newly exposed silicon/ledge 46 as a seed. Thus, the capacitance value of a backplane 32 can be decreased, while the control of the threshold voltage is retained.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2000277745A

公开(公告)日：2000-10-06

申请号：JP2000069146

申请日：2000-03-13

Applicant: IBM

Inventor： KEVIN K CHAN ,  GUY M COEN ,  EUAN TOWER ,  HON-SAN P WAN

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To obtain a method for forming a double-gate MOSFET structure in which the thickness of an oxide can be properly controlled and the upper and lower gate positions can be matched, and a structure for this. SOLUTION: This method for manufacturing a double-gate MOSFET structure comprises a step of forming a laminated structure having a monocrystal silicon channel layer 5 and an insulating oxide and nitride layer, a step of forming an opening in the laminated structure, a step for forming a source and drain region 9 in the opening, a step of removing the laminated structure part by part which is not covered with a mask, a step of removing the mask and the insulating oxide and nitride layer, and for leaving the channel layer 5 suspended from the source/drain region, a step of forming an oxide layer 11, and for covering the source/drain region and the channel layer, and a step for forming a double-gate conductor 12 on the oxide layer 11, so that a first conductor and a second conductor can be respectively included at the first side and second side of the channel layer 5.