公开(公告)号：JP2006041526A

公开(公告)日：2006-02-09

申请号：JP2005213971

申请日：2005-07-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DE SOUZA JOEL P ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/76243 ,  H01L21/76267 ,  H01L27/1203 ,  H01L27/1207

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a device on a crystal of orientation which brings about optimal performance by providing separation by an oxygen implantation (SIMOX) method for the formation of a flat hybrid orientation semiconductor on insulator (SOI) substrate having a crystal of different orientation. SOLUTION: A method comprises steps of: selecting a substrate having a lower semiconductor layer having first crystal orientation separated from an upper semiconductor layer having second crystal orientation by a thin insulating layer; replacing the upper semiconductor layer of a selected region with epitaxial growth semiconductor having the first crystal orientation; (i) forming a padding insulating region in an epitaxial growth semiconductor material and (ii) thickening an insulating layer under the upper semiconductor layer using ion implantation and annealing methods; and forming a hybrid orientation substrate in which two semiconductor materials of different crystal orientation have substantially identical thickness and are arranged on the common padding insulating layer. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过提供通过氧注入（SIMOX）方法分离以形成绝缘体上的平坦混合取向半导体（SOI）的方向来制造取向晶体的装置的方法，该方法产生最佳性能 ）衬底具有不同取向的晶体。 解决方案：一种方法包括以下步骤：通过薄绝缘层，选择具有从具有第二晶体取向的上半导体层分离的具有第一晶体取向的下半导体层的衬底; 用具有第一晶体取向的外延生长半导体代替所选区域的上半导体层; （i）在外延生长半导体材料中形成填充绝缘区域，和（ii）使用离子注入和退火方法使上半导体层下方的绝缘层增厚; 以及形成混合取向基板，其中两个不同晶体取向的半导体材料具有基本上相同的厚度并且布置在公共衬垫绝缘层上。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006135319A

公开(公告)日：2006-05-25

申请号：JP2005309279

申请日：2005-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAINE C BOYD ,  CAI JUAN ,  KEVIN K CHAN ,  MOONEY PATRICIA M ,  KERN LIM

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/7842 ,  Y10S438/938

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure for use in n-type and p-type MOSFET devices, and the method of manufacturing the same.
SOLUTION: A semiconductor structure is formed such that the layer structure of a wafer region by which an n-type MOSFET is manufactured is different from the layer structure of a wafer region by which a p-type MOSFET is manufactured. First, the structure is manufactured by forming a damage region on the front surface of an Si content substrate by ion implantation of a light atom such as He. Then, strained SiGe alloy is formed on the Si content substrate comprising the damage region. Then, the strained SiGe alloy is made to ease substantially by strained relaxation resulting from defect using an anneal step. Then, a strained semiconductor cap of strained Si etc. is formed on the strained SiGe alloy.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于n型和p型MOSFET器件的半导体结构及其制造方法。 解决方案：形成半导体结构，使得制造n型MOSFET的晶片区域的层结构不同于制造p型MOSFET的晶片区域的层结构。 首先，通过用诸如He的光原子的离子注入在Si含量衬底的前表面上形成损伤区域来制造结构。 然后，在包含损伤区域的Si含量基板上形成应变SiGe合金。 然后，使应变SiGe合金基本上通过使用退火步骤的缺陷导致的应变弛豫来简化。 然后，在应变SiGe合金上形成应变Si等的应变半导体盖。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005311367A

公开(公告)日：2005-11-04

申请号：JP2005119125

申请日：2005-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DORIS BRUCE B ,  GUARINI KATHRYN W ,  LEONG MEIKEI ,  NARASIMHA SHREESH ,  REZNICEK ALEXANDER ,  KERN LIM ,  SADANA DEVENDRA K ,  SHI LEATHEN ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor device formed on a substrate having different crystal orientation.
SOLUTION: A method of forming a hybrid substrate containing strained Si and a strained Si containing hybrid substrate formed by this method are provided. In the present invention, a strained Si layer is formed on a semiconductor material, a second semiconductor layer, or both of them. According to the present invention, the strained Si layer has the same crystal orientation as either of a regrown semiconductor layer or the second semiconductor layer. This method provides the hybrid substrate wherein at least one of device layers contains the strained Si.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供形成在具有不同晶体取向的基板上的集成半导体器件。 解决方案：提供一种形成含有应变Si的混合基板和通过该方法形成的包含应变的含Si混合基板的方法。 在本发明中，在半导体材料，第二半导体层或它们两者上形成应变Si层。 根据本发明，应变Si层具有与重新生长的半导体层或第二半导体层中的任一个相同的晶体取向。 该方法提供混合基板，其中装置层中的至少一个包含应变Si。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004207714A

公开(公告)日：2004-07-22

申请号：JP2003413993

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  GUY M COEN ,  IEONG MEIKEI ,  ROY RONNEN A ,  SOLOMON PAUL M ,  YANG MIN

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate field effect transistor (DGFET) structure which can noticeably reduce the parasitic capacitance under its source/drain region, and its manufacturing method.
SOLUTION: This double-gate field effect transistor (DGFET) adopts new two means for reducing the parasitic capacitance under its source/drain region. One means is as follows: a silicon region outside a gate is converted into an oxide 44, while a silicon/ledge 46 adjacent to the gate 58 is protected with a first spacer having a first width. This oxidation can be performed easily by means of implantation of self-aligned oxygen ions or other ions. The other means is to have the first spacer removed and replaced with a second spacer 48 which has a width smaller than that of the first one, and a new silicon source/drain region 60 formed under a self-aligned isolation region 56 by lateral selective full overgrowth, by using the newly exposed silicon/ledge 46 as a seed. Thus, the capacitance value of a backplane 32 can be decreased, while the control of the threshold voltage is retained.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004207726A

公开(公告)日：2004-07-22

申请号：JP2003421646

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SOLOMON PAUL M ,  KEVIN K CHAN ,  HANAFI HUSSEIN I

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/78648

Abstract: PROBLEM TO BE SOLVED: To provide a dual gate field-effect transistor (DGFET) structure, with a significantly reduced parasitic capacity in the source/drain region and its formation method.
SOLUTION: This dual-gate field-effect transistor reduces the parasitic capacity in the DGFET structure by being provided with a self-aligned isolation region 44. Furthermore, the parasitic capacity of the structure is further reduced, by enabling substantial oxidization to occur at a back gate, which is made possible by coating a silicon contained channel 18.
COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供双栅极场效应晶体管（DGFET）结构，其在源极/漏极区域中的显着降低的寄生电容及其形成方法。 解决方案：该双栅极场效应晶体管通过提供自对准隔离区域44来减小DGFET结构中的寄生电容。此外，通过使得能够实质上的氧化到 发生在后门，其通过涂覆含硅通道18而成为可能。（C）2004年，JPO和NCIPI

公开(公告)号：JP2000277745A

公开(公告)日：2000-10-06

申请号：JP2000069146

申请日：2000-03-13

Applicant: IBM

Inventor： KEVIN K CHAN ,  GUY M COEN ,  EUAN TOWER ,  HON-SAN P WAN

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To obtain a method for forming a double-gate MOSFET structure in which the thickness of an oxide can be properly controlled and the upper and lower gate positions can be matched, and a structure for this. SOLUTION: This method for manufacturing a double-gate MOSFET structure comprises a step of forming a laminated structure having a monocrystal silicon channel layer 5 and an insulating oxide and nitride layer, a step of forming an opening in the laminated structure, a step for forming a source and drain region 9 in the opening, a step of removing the laminated structure part by part which is not covered with a mask, a step of removing the mask and the insulating oxide and nitride layer, and for leaving the channel layer 5 suspended from the source/drain region, a step of forming an oxide layer 11, and for covering the source/drain region and the channel layer, and a step for forming a double-gate conductor 12 on the oxide layer 11, so that a first conductor and a second conductor can be respectively included at the first side and second side of the channel layer 5.

公开(公告)号：JP2006019725A

公开(公告)日：2006-01-19

申请号：JP2005182416

申请日：2005-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  CHU JACK O ,  KERN LIM ,  SHI LEATHEN

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

Abstract: PROBLEM TO BE SOLVED: To provide a formation method for a heterostructure that can separate the fact that high strain is preferred in a strain Si layer and a Ge content in a low layer.
SOLUTION: A first multilayered structure 10 of a strained Si layer 14 and tensile strain SiGe alloy layer 16 constitute on a relaxation SiGe alloy layer 12. Then, a second multilayered structure 18, including an insulating layer 20, is formed on a substrate 22 and jointed with the first multilayered structure 10. After the insulating layer 20 and the SiGe alloy layer 16 are jointed, the relaxing SiGe alloy layer 12 is completely removed.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种异质结构的形成方法，其可以分离应变Si层中的高应变和低层中的Ge含量的事实。 解决方案：应变Si层14和拉伸应变SiGe合金层16的第一多层结构10构成弛豫SiGe合金层12.然后，在第一多层结构18上形成包括绝缘层20的第二多层结构18 基板22并与第一多层结构10连接。在绝缘层20和SiGe合金层16接合之后，完全去除弛豫SiGe合金层12。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2002353246A

公开(公告)日：2002-12-06

申请号：JP2002110367

申请日：2002-04-12

Applicant: IBM

Inventor： CYRILLE CABRAL JR ,  KEVIN K CHAN ,  COHEN GUY MOSHE ,  GUARINI KATHRYN WILDER ,  LAVOIE CHRISTIAN ,  PAUL MICHAEL SOLOMON ,  ZHANG YING

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned silicide process applicable to contacting silicon, sidewall, source, and drain. SOLUTION: A method (and a structure formed by using this method) to form a metal silicide contact on a non-planar silicon-containing area which limits the silicon consumption at a silicon-containing area includes: forming a blanket metal layer over the silicon-containing area, forming a silicon layer over the metal layer, performing an selective and anisotropical etching of the silicon layer against the metal, forming a metal silicon alloy by reacting the metal and silicon at a first temperature, etching away any unreacted metal layer, forming a metal-Si2 alloy by annealing at a second temperature, and selectively etching away any unreacted silicon layer.

公开(公告)号：BR112012031951A2

公开(公告)日：2018-03-06

申请号：BR112012031951

申请日：2011-06-10

Applicant: IBM

Inventor： ABHISHEK DUBE ,  DAE-GYU PARK ,  JEFFREY B JOHNSON ,  JINGHONG LI ,  JUDSON R HOLT ,  KEVIN K CHAN ,  ZHENGMAO ZHU

IPC: H01L21/336 ,  H01L29/78

公开(公告)号：HK1041678B

公开(公告)日：2005-12-09

申请号：HK02103371

申请日：2002-05-03

Applicant: IBM

Inventor： KEVIN K CHAN ,  CHRISTOPHER JHANES ,  LEATHEN SHI ,  JAMES L SPEIDELL ,  JAMES F ZIEGLER

IPC: B81B20060101 ,  B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  H01P20060101 ,  H03D7/00 ,  H03H3/007 ,  H03H9/10 ,  H03H9/24 ,  H03H9/46 ,  H04B1/26