公开(公告)号：DE112021000410T5

公开(公告)日：2022-12-22

申请号：DE112021000410

申请日：2021-02-11

Applicant: IBM

Inventor： STERBLING SVEN ,  HABERMANN CHRISTIAN ,  VITTAL SACHIN LINGADAHALLI

IPC: G06F15/163 ,  G06F15/167 ,  H04L67/5682

Abstract: Ein Verfahren, ein Computersystem und ein Computerprogrammprodukt zur Ausführung eines zustandslosen Dienstes auf einem Knoten in einer Betriebslast-Ausführungsumgebung werden bereitgestellt. Die vorliegende Erfindung kann für jeden Knoten ein Definieren eines Betriebslastcontainers umfassen, der eine Cache-Komponente eines Cache-Netzes umfasst. Die vorliegende Erfindung kann nach dem Empfangen einer Zustandsanforderung von einem zustandslosen anfordernden Dienst aus einer der Cache-Komponenten des Cache-Netzes in einem Ausführungscontainer ein Ermitteln umfassen, ob ein angeforderter Zustand in der Cache-Komponente eines zugehörigen Ausführungscontainers vorhanden ist. Die vorliegende Erfindung kann nach einem Cache-Fehltreffer ein Rundsenden der Zustandsanforderung an andere Cache-Komponenten des Cache-Netzes, ein Ermitteln, durch die anderen Cache-Komponenten, ob der angeforderte Zustand in jeweiligen Caches vorhanden ist, und nachdem eine beliebige Cache-Komponente den angeforderten Zustand erkennt, ein Senden des angeforderten Zustands an den anfordernden Dienst unter Verwendung eines Protokolls für die Datenübertragung umfassen.

公开(公告)号：GB2507758A

公开(公告)日：2014-05-14

申请号：GB201220120

申请日：2012-11-08

Applicant: IBM

Inventor： TAST HANS-WERNER ,  RECKTENWALD MARTIN ,  HABERMANN CHRISTIAN ,  JACOBI CHRISTIAN

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0846 ,  G06F12/0875 ,  G06F12/0897

Abstract: A cache hierarchy for a data processing system comprises a first level instruction cache 12, a first level data cache 14, a second level instruction cache 22, a second level data cache 24 and a unified third level cache 30. The first level data cache makes requests to read data from both the level two caches. If the data is in the second level instruction cache and the request is for exclusive access, then the second level instruction cache requests exclusive ownership of the cache line from the third level cache and the cache line in the second level instruction cache is promoted to exclusive ownership. If the data is in neither second level cache, then the request is sent to the third level cache. In this case, the data is placed in the second and first level data caches.

公开(公告)号：AU2021246978A1

公开(公告)日：2022-09-01

申请号：AU2021246978

申请日：2021-02-11

Applicant: IBM

Inventor： STERBLING SVEN ,  HABERMANN CHRISTIAN ,  VITTAL SACHIN LINGADAHALLI

IPC: G06F9/50

Abstract: A method, computer system, and a computer program product for execution of a stateless service on a node (204,206,208) in a workload execution environment is provided. The method may include defining for each node (204, 206, 208) a workload container (210, 216, 222, 228) including a cache component (214, 220, 226, 232) of a cache-mesh. The method may include, upon receiving a state request from a stateless requesting service from one of the cache components (214, 220, 226, 232) of the cache-mesh in an execution container(210, 216, 222, 228), determining whether a requested state is present in the cache component (214, 220, 226, 232) of a related execution container(210, 216, 222, 228). The method may include, upon a cache miss, broadcasting the state request to other cache components (214, 220, 226, 232) of the cache-mesh, determining, by the other cache components (214, 220, 226, 232), whether the requested state is present in respective caches, and upon any cache component (214, 220, 226, 232) identifying the requested state, sending the requested state to the requesting service using a protocol for communication.

公开(公告)号：GB2516477A

公开(公告)日：2015-01-28

申请号：GB201313191

申请日：2013-07-24

Applicant: IBM

Inventor： HABERMANN CHRISTIAN ,  RECKTENWALD MARTIN ,  KOCH GERRIT ,  TAST HANS-WERNER ,  JACOBI CHRISTIAN

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0897 ,  G06F12/1045 ,  G06F12/123

Abstract: A multi-level cache hierarchy structure with a first level, Ll, cache, being connected to a second level, L2, cache split into a L2 data cache directory and a L2 instruction cache. The L2 data cache directory comprises directory entries comprising information of data currently stored in the L1 cache. The first level cache is virtually indexed while the second and third levels are physically indexed, and allocating counter bits in a directory entry of tie L2 data cache directory for storing a counter number. The directory entry corresponds to at least one first Ll cache line; performing a first search in the Ll cache for a requested virtual memory address, wherein the virtual memory address corresponds to a physical memory address tag at a second L1 cache line. The directory entry may include least recently used bits to indicate cache lines for data replacement. The directory may be updated with a synonym index.

公开(公告)号：GB2507759A

公开(公告)日：2014-05-14

申请号：GB201220121

申请日：2012-11-08

Applicant: IBM

Inventor： TAST HANS-WERNER ,  RECKTENWALD MARTIN ,  HABERMANN CHRISTIAN ,  JACOBI CHRISTIAN

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0897

Abstract: A hierarchical cache 1 for a data processing system comprises a third level L3 cache 300, a second level L2 cache 200 and a first level L1 cache100. The first level cache is divided into a level one instruction L1i cache 10 and a level one data L1d cache 20. Similarly, the second level cache is divided into a level two instruction (L2i) cache 30 and a level two data (L2d) cache 40. The level three cache is a unified cache. The L1i cache can request data from the L2i cache, which can request data from the L3 cache. The L1d cache can request data from the L2i cache and the L3 cache. The L1 caches are indexed with virtual addresses, whereas the L2 and L3 caches are indexed with physical addresses. The L2 caches translate real addresses to virtual addresses.