公开(公告)号：GB2512888A

公开(公告)日：2014-10-15

申请号：GB201306497

申请日：2013-04-10

Applicant: IBM

Inventor： RUF JUERGEN ,  GREINER CARSTEN ,  KOCH GERRIT ,  WERNER KEN

IPC: G06F17/50 ,  G06F11/36

Abstract: A verification assistance method is used for reviewing verifica­tion data for a digital circuit design. In order to reduce the time and effort spent on the verification, the verification assistance method stores user operation information (SB4) and recommends a user operation based on said user opera­tion information (SB1). In particular the user operation information relates to a position of a user operation in a previous sequence of user operations and the recommended user operation may correspond to an operation in the previous sequence.

公开(公告)号：GB2516477A

公开(公告)日：2015-01-28

申请号：GB201313191

申请日：2013-07-24

Applicant: IBM

Inventor： HABERMANN CHRISTIAN ,  RECKTENWALD MARTIN ,  KOCH GERRIT ,  TAST HANS-WERNER ,  JACOBI CHRISTIAN

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0897 ,  G06F12/1045 ,  G06F12/123

Abstract: A multi-level cache hierarchy structure with a first level, Ll, cache, being connected to a second level, L2, cache split into a L2 data cache directory and a L2 instruction cache. The L2 data cache directory comprises directory entries comprising information of data currently stored in the L1 cache. The first level cache is virtually indexed while the second and third levels are physically indexed, and allocating counter bits in a directory entry of tie L2 data cache directory for storing a counter number. The directory entry corresponds to at least one first Ll cache line; performing a first search in the Ll cache for a requested virtual memory address, wherein the virtual memory address corresponds to a physical memory address tag at a second L1 cache line. The directory entry may include least recently used bits to indicate cache lines for data replacement. The directory may be updated with a synonym index.