公开(公告)号：WO2007039412A3

公开(公告)日：2007-10-04

申请号：PCT/EP2006066249

申请日：2006-09-11

Applicant: IBM ,  IBM UK ,  ABERNATHY CHRISTOPHER MICHAEL ,  DEMENT JONATHAN JAMES ,  HALL RONALD ,  PHILHOWER ROBERT ALAN ,  SHIPPY DAVID

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  DEMENT JONATHAN JAMES ,  HALL RONALD ,  PHILHOWER ROBERT ALAN ,  SHIPPY DAVID

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3237 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/3867 ,  Y02D10/128 ,  Y02D10/152

Abstract: A system and method for dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.

Abstract translation: 介绍了一种用于处理器设计中的动态功率管理的系统和方法。 流水线级的失速检测逻辑检测到失速条件，并向空闲检测逻辑发送信号以关闭流水线的寄存器时钟。 失速检测逻辑还监测下游流水线级的失速状况，并且当下游流水线级也处于失速状态时，指示空闲检测逻辑门控关闭流水线级的寄存器。 另外，当流水线级的失速检测逻辑检测到来自下游流水线级或来自它自己的流水线单元的失速条件时，流水线级的失速检测逻辑通知上游流水线级关闭其时钟，从而节省更多功率 。

公开(公告)号：GB2494331A

公开(公告)日：2013-03-06

申请号：GB201221747

申请日：2011-05-04

Applicant: IBM

Inventor： HALL RONALD ,  SINHAROY BALARAM ,  LE HUNG QUI ,  SILVERA RAUL ESTEBAN

IPC: G06F9/38 ,  G06F9/30

Abstract: Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

公开(公告)号：DE112011100715T8

公开(公告)日：2013-03-28

申请号：DE112011100715

申请日：2011-05-04

Applicant: IBM

Inventor： HALL RONALD ,  SINHAROY BALARAM ,  SILVERA RAUL ESTEBAN ,  LE HUNG QUI

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38

公开(公告)号：AT441148T

公开(公告)日：2009-09-15

申请号：AT07727376

申请日：2007-03-27

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER ,  FEISTE KURT ,  VAN NORSTRAND ALBERT ,  HALL RONALD

IPC: G06F9/38

Abstract: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.

公开(公告)号：DE112011100715T5

公开(公告)日：2013-01-24

申请号：DE112011100715

申请日：2011-05-04

Applicant: IBM

Inventor： HALL RONALD ,  HAROY BALARAM ,  SILVERA RAUL ESTEBAN ,  LE HUNG QUI

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38

Abstract: Es werden Mechanismen zum Abladen einer Arbeitslast eines Haupt-Thread auf einen Hilfs-Thread bereitgestellt. Die Mechanismen empfangen eine Anweisung eines Haupt-Thread zum Verzweigen zu einem Hilfs-Thread in einer Abrufeinheit eines Prozessors des Datenverarbeitungssystems. Die Anweisung zum Verzweigen zu einem Hilfs-Thread verständigt Hardware des Prozessors, damit diese nach einem bereits erzeugten Leerlauf-Thread sucht, der als Hilfs-Thread verwendet werden kann. Auf Hardware ausgeführte allgegenwärtige Thread-Steuerlogik ermittelt, ob ein oder mehrere bereits erzeugte Leerlauf-Threads zur Verwendung als Hilfs-Thread verfügbar sind. Die auf Hardware ausgeführte allgegenwärtige Thread-Steuerlogik wählt aus dem einen bzw. den mehreren bereits erzeugten Leerlauf-Threads einen Leerlauf-Thread aus, wenn ermittelt wird, dass ein oder mehrere bereits erzeugte Leerlauf-Threads zur Verwendung als Hilfs-Thread verfügbar sind, um dadurch den Hilfs-Thread bereitzustellen. Außerdem lädt die auf Hardware ausgeführte allgegenwärtige Thread-Steuerlogik einen Teil einer Arbeitslast des Haupt-Thread auf einen Hilfs-Thread ab.

公开(公告)号：DE602007002189D1

公开(公告)日：2009-10-08

申请号：DE602007002189

申请日：2007-03-27

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  FEISTE KURT ALAN ,  VAN NORSTRAND ALBERT JAMES ,  HALL RONALD

IPC: G06F9/38

Abstract: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.