公开(公告)号：WO2007039412A3

公开(公告)日：2007-10-04

申请号：PCT/EP2006066249

申请日：2006-09-11

Applicant: IBM ,  IBM UK ,  ABERNATHY CHRISTOPHER MICHAEL ,  DEMENT JONATHAN JAMES ,  HALL RONALD ,  PHILHOWER ROBERT ALAN ,  SHIPPY DAVID

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  DEMENT JONATHAN JAMES ,  HALL RONALD ,  PHILHOWER ROBERT ALAN ,  SHIPPY DAVID

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3237 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/3867 ,  Y02D10/128 ,  Y02D10/152

Abstract: A system and method for dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.

Abstract translation: 介绍了一种用于处理器设计中的动态功率管理的系统和方法。 流水线级的失速检测逻辑检测到失速条件，并向空闲检测逻辑发送信号以关闭流水线的寄存器时钟。 失速检测逻辑还监测下游流水线级的失速状况，并且当下游流水线级也处于失速状态时，指示空闲检测逻辑门控关闭流水线级的寄存器。 另外，当流水线级的失速检测逻辑检测到来自下游流水线级或来自它自己的流水线单元的失速条件时，流水线级的失速检测逻辑通知上游流水线级关闭其时钟，从而节省更多功率 。

公开(公告)号：DE112012000965T8

公开(公告)日：2014-06-05

申请号：DE112012000965

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH ,  BROWN MARY DOUGLASS

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00

公开(公告)号：DE602007002189D1

公开(公告)日：2009-10-08

申请号：DE602007002189

申请日：2007-03-27

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  FEISTE KURT ALAN ,  VAN NORSTRAND ALBERT JAMES ,  HALL RONALD

IPC: G06F9/38

Abstract: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.

公开(公告)号：GB2502222A

公开(公告)日：2013-11-20

申请号：GB201314787

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  BROWN MARY DOUGLASS ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

公开(公告)号：DE112012000965T5

公开(公告)日：2013-11-14

申请号：DE112012000965

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH ,  BROWN MARY DOUGLASS

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00

Abstract: Ein System und ein Prozess zum Verwalten von Thread-Übergängen kann die Fähigkeit beinhalten, zu ermitteln, dass ein Übergang im Hinblick auf die relative Nutzung von zwei Datenregistersätzen vorzunehmen ist, und auf der Grundlage der Übergangsermittlung zu ermitteln, ob Thread-Daten in mindestens einem der Datenregistersätze auf Register der zweiten Ebene zu verschieben sind. Das System und der Prozess können zudem die Fähigkeit beinhalten, die Thread-Daten auf der Grundlage der Verschiebeermittlung von mindestens einem Datenregistersatz auf Register der zweiten Ebene zu verschieben.

公开(公告)号：GB2502222B

公开(公告)日：2014-04-09

申请号：GB201314787

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  BROWN MARY DOUGLASS ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.