中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.023 seconds)

    Method, system, and program for managing grid computing environment
    2.
    发明专利
    Method, system, and program for managing grid computing environment 有权
    用于管理网格计算环境的方法，系统和程序

    公开(公告)号：JP2007102789A

    公开(公告)日：2007-04-19

    申请号：JP2006270476

    申请日：2006-10-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： SEAMAN JAMES WESLEY ,  HAMILTON RICK A II ,  JOSEPH JOSHY ,  DAWSON CHRISTOPHER J

    IPC: G06F9/50

    CPC classification number: H04L41/5009 ,  G06F9/5072 ,  G06F11/3409 ,  G06F11/3466 ,  H04L41/147 ,  H04L41/5032 ,  H04L67/10

    Abstract: PROBLEM TO BE SOLVED: To provide a method and system for managing a grid computing environment.
    SOLUTION: Performance data is captured periodically from resources and groups of resources in the grid computing environment, and stored in a content-addressable data repository from which it can be accessed in response to an arbitrarily complex query in regard to specifics of particular jobs or job portions, particular resources utilized, grid architecture, application environment, concurrent jobs or job portions and the like. The data repository can be distributed or divided in regard to grid environment architecture, security domains or the like and each portion or division can be implemented in a modular fashion including an accounting and statistics management module or computing engines for performing particular desired analyses or functions.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于管理网格计算环境的方法和系统。 解决方案：性能数据是从网格计算环境中的资源和资源组中定期捕获的，并存储在可内容寻址的数据存储库中，从而可以根据具体情况的任意复杂查询来访问性能数据库 作业或作业部分，所利用的特定资源，网格架构，应用环境，并发作业或作业部分等。 数据存储库可以根据网格环境架构，安全域等进行分发或划分，每个部分或部分可以以包括会计和统计管理模块或用于执行特定期望分析或功能的计算引擎的模块化方式来实现。 版权所有（C）2007，JPO＆INPIT

    METHODOLOGY FOR EMULATION OF MULTI-THREADED PROCESSES IN A SINGLE-THREADED OPERATING SYSTEM
    3.
    发明专利
    METHODOLOGY FOR EMULATION OF MULTI-THREADED PROCESSES IN A SINGLE-THREADED OPERATING SYSTEM 未知

    公开(公告)号：CA2283046A1

    公开(公告)日：2000-04-02

    申请号：CA2283046

    申请日：1999-09-23

    Applicant: IBM

    Inventor： FORSMAN STEPHANIE M ,  HAMILTON RICK A II ,  MEHTA CHETAN ,  PATEL MAULIN I

    IPC: G06F9/455 ,  G06F9/48 ,  G06F9/46

    Abstract: To emulate multi-threaded processing in an operating system supporting only single-threaded processes and single-level interrupts, the processor timer is started with a selected time-out period during execution of a master code thread. Processing of the master code thread proceeds until the timer interrupt, at which time the operating system timer interrupt service routine (ISR) transfers execution control to a slave code thread or slave code thread component. The slave code thread or component is executed in its entirety, at which time the timer is reset and execution control is returned to the master code thread, where processing resumes at the point during which the timer interrupt was asserted. To minimize disruption of the master code thread execution, a maximum latency should be enforced on the slave code thread, which may be accomplished by breaking the slave code thread into multiple components. The timer ISR maintains an index of the predetermined starting points within the slave code thread(s) with a pointer identifying the next slave code thread component to be selected when the timer interrupt is asserted. Processing thus alternates between the master code thread and the slave code thread or components, with different slave code thread components being selected in round-robin fashion. The duty cycle between the master code thread and the slave code thread or components may be varied by selection of the timeout period and the maximum latency allowed to slave code thread processing.

    METHODOLOGY FOR EMULATION OF MULTI-THREADED PROCESSES IN A SINGLE-THREADED OPERATING SYSTEM
    4.
    发明专利
    METHODOLOGY FOR EMULATION OF MULTI-THREADED PROCESSES IN A SINGLE-THREADED OPERATING SYSTEM 未知

    公开(公告)号：CA2283046C

    公开(公告)日：2003-07-15

    申请号：CA2283046

    申请日：1999-09-23

    Applicant: IBM

    Inventor： FORSMAN STEPHANIE M ,  PATEL MAULIN I ,  HAMILTON RICK A II ,  MEHTA CHETAN

    IPC: G06F9/455 ,  G06F9/48 ,  G06F9/46

    Abstract: To emulate multi-threaded processing in an operating system supporting only single-threaded processes and single-level interrupts, the processor timer is started with a selected time-out period during execution of a master code thread. Processing of the master code thread proceeds until the timer interrupt, at which time the operating system timer interrupt service routine (ISR) transfers execution control to a slave code thread or slave code thread component. The slave code thread or component is executed in its entirety, at which time the timer is reset and execution control is returned to the master code thread, where processing resumes at the point during which the timer interrupt was asserted. To minimize disruption of the master code thread execution, a maximum latency should be enforced on the slave code thread, which may be accomplished by breaking the slave code thread into multiple components. The timer ISR maintains an index of the predetermined starting points within the slave code thread(s) with a pointer identifying the next slave code thread component to be selected when the timer interrupt is asserted. Processing thus alternates between the master code thread and the slave code thread or components, with different slave code thread components being selected in round-robin fashion. The duty cycle between the master code thread and the slave code thread or components may be varied by selection of the time- out period and the maximum latency allowed to slave code thread processing.

Patent Agency Ranking