公开(公告)号：CA2283046A1

公开(公告)日：2000-04-02

申请号：CA2283046

申请日：1999-09-23

Applicant: IBM

Inventor： FORSMAN STEPHANIE M ,  HAMILTON RICK A II ,  MEHTA CHETAN ,  PATEL MAULIN I

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/46

Abstract: To emulate multi-threaded processing in an operating system supporting only single-threaded processes and single-level interrupts, the processor timer is started with a selected time-out period during execution of a master code thread. Processing of the master code thread proceeds until the timer interrupt, at which time the operating system timer interrupt service routine (ISR) transfers execution control to a slave code thread or slave code thread component. The slave code thread or component is executed in its entirety, at which time the timer is reset and execution control is returned to the master code thread, where processing resumes at the point during which the timer interrupt was asserted. To minimize disruption of the master code thread execution, a maximum latency should be enforced on the slave code thread, which may be accomplished by breaking the slave code thread into multiple components. The timer ISR maintains an index of the predetermined starting points within the slave code thread(s) with a pointer identifying the next slave code thread component to be selected when the timer interrupt is asserted. Processing thus alternates between the master code thread and the slave code thread or components, with different slave code thread components being selected in round-robin fashion. The duty cycle between the master code thread and the slave code thread or components may be varied by selection of the timeout period and the maximum latency allowed to slave code thread processing.

公开(公告)号：CA2283046C

公开(公告)日：2003-07-15

申请号：CA2283046

申请日：1999-09-23

Applicant: IBM

Inventor： FORSMAN STEPHANIE M ,  PATEL MAULIN I ,  HAMILTON RICK A II ,  MEHTA CHETAN

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/46

Abstract: To emulate multi-threaded processing in an operating system supporting only single-threaded processes and single-level interrupts, the processor timer is started with a selected time-out period during execution of a master code thread. Processing of the master code thread proceeds until the timer interrupt, at which time the operating system timer interrupt service routine (ISR) transfers execution control to a slave code thread or slave code thread component. The slave code thread or component is executed in its entirety, at which time the timer is reset and execution control is returned to the master code thread, where processing resumes at the point during which the timer interrupt was asserted. To minimize disruption of the master code thread execution, a maximum latency should be enforced on the slave code thread, which may be accomplished by breaking the slave code thread into multiple components. The timer ISR maintains an index of the predetermined starting points within the slave code thread(s) with a pointer identifying the next slave code thread component to be selected when the timer interrupt is asserted. Processing thus alternates between the master code thread and the slave code thread or components, with different slave code thread components being selected in round-robin fashion. The duty cycle between the master code thread and the slave code thread or components may be varied by selection of the time- out period and the maximum latency allowed to slave code thread processing.